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Jordi Madrenas
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2020 – today
- 2024
- [j23]Bernardo Vallejo Mancero
, Sergio Faci-Lázaro, Mireya Zapata
Real-time hardware emulation of neural cultures: A comparative study of in vitro, in silico and in duris silico models. Neural Networks 179: 106593 (2024) - [c60]Satoshi Moriya, Hideaki Yamamoto, Masaya Ishikawa, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas, Shigeo Sato:
Design of Mixed-Signal LSI with Analog Spiking Neural Network and Digital Inference Circuits for Reservoir Computing. IJCNN 2024: 1-6 - 2023
- [c59]Jordi Madrenas
Real-Time Adaptive Physical Sensor Processing with SNN Hardware. ICANN (5) 2023: 423-434 - [c58]Sasan Nikseresht
CMOS Adaptive Optical Wireless Receiver for Ultra-Low-Power IoT Applications. MWSCAS 2023: 787-791 - 2022
- [c57]Bernardo Vallejo Mancero
Real-Time Display of Spiking Neural Activity of SIMD Hardware Using an HDMI Interface. ICANN (3) 2022: 728-739 - [c56]Satoshi Moriya, Hideaki Yamamoto, Shigeo Sato, Yasushi Yuminaka, Yoshihiko Horio, Jordi Madrenas:
A Fully Analog CMOS Implementation of a Two-variable Spiking Neuron in the Subthreshold Region and its Network Operation. IJCNN 2022: 1-7 - [c55]Mireya Zapata
Real-Time Monitoring Tool for SNN Hardware Architecture. WIVACE 2022: 291-302 - 2021
- [j22]Juan Valle
Manufacturing Issues of BEOL CMOS-MEMS Devices. IEEE Access 9: 83149-83162 (2021) - [j21]Josep Maria Sánchez-Chiva
A Test Setup for the Characterization of Lorentz-Force MEMS Magnetometers. IEEE Open J. Circuits Syst. 2: 587-596 (2021) - [c54]Shigeo Sato
A Subthreshold Spiking Neuron Circuit Based on the Izhikevich Model. ICANN (5) 2021: 177-181 - [c53]Josep Angel Oltra
Hardware-Software Co-Design for Efficient and Scalable Real-Time Emulation of SNNs on the Edge. ISCAS 2021: 1-5 - 2020
- [j20]Josep Maria Sánchez-Chiva
A CMOS-MEMS BEOL 2-axis Lorentz-Force Magnetometer with Device-Level Offset Cancellation. Sensors 20(20): 5899 (2020) - [j19]Diana Mata-Hernandez
Resonant MEMS Pressure Sensor in 180 nm CMOS Technology Obtained by BEOL Isotropic Etching. Sensors 20(21): 6037 (2020) - [c52]Jordi Madrenas, Mireya Zapata
Towards Efficient and Adaptive Cyber Physical Spiking Neural Integrated Systems. ICECS 2020: 1-4 - [c51]Josep Maria Sánchez-Chiva
A test setup for the characterization of Lorentz-force MEMS magnetometers. ICECS 2020: 1-4
2010 – 2019
- 2019
- [j18]Giovanny Sánchez
LEGION-based image segmentation by means of spiking neural networks using normalized synaptic weights implemented on a compact scalable neuromorphic architecture. Neurocomputing 352: 106-120 (2019) - [c50]Mireya Zapata
Axonal Delay Controller for Spiking Neural Networks Based on FPGA. AHFE (14) 2019: 284-292 - [c49]Jordi Madrenas
Design Considerations for Analog LCMOS Harvest-Use Integrated Signal Processing. ISCAS 2019: 1-5 - 2018
- [j17]T. A. Athul Sripad, Giovanny Sánchez
SNAVA - A real-time multi-FPGA multi-model spiking neural network simulation architecture. Neural Networks 97: 28-45 (2018) - [j16]Piotr Michalik
Experiments on MEMS Integration in 0.25 μm CMOS Process. Sensors 18(7): 2111 (2018) - [c48]Mireya Zapata
Efficient Configuration for a Scalable Spiking Neural Network Platform by means of a Synchronous Address Event Representation bus. AHS 2018: 241-248 - [c47]C. Bauza, Josep Maria Sánchez-Chiva
Optimizing Power Consumption vs. Linearization in CMFB Amplifiers with Source Degeneration. ICECS 2018: 269-272 - 2017
- [c46]Hisanao Akima, Susumu Kawakami, Jordi Madrenas
Complexity Reduction of Neural Network Model for Local Motion Detection in Motion Stereo Vision. ICONIP (6) 2017: 830-839 - [c45]Javier Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
Self-adaptive hardware architecture with parallel processing capabilities and dynamic reconfiguration. ARM@Middleware 2017: 4:1-4:7 - 2016
- [j15]Hisanao Akima, Yasuhiro Katayama, Masao Sakuraba
CMOS Majority Circuit with Large Fan-In. IEICE Trans. Electron. 99-C(9): 1056-1064 (2016) - [j14]Taho Dorta, Mireya Zapata
AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation. Neurocomputing 171: 1684-1690 (2016) - [j13]María-Dolores Cubells-Beltrán
Integration of GMR Sensors with Different Technologies. Sensors 16(6): 939 (2016) - [c44]Mireya Zapata
Synfire Chain Emulation by Means of Flexible SNN Modeling on a SIMD Multicore Architecture. ICANN (1) 2016: 365-373 - [c43]Mireya Zapata
Compact Associative Memory for AER Spike Decoding in FPGA-Based Evolvable SNN Emulation. ICANN (1) 2016: 399-407 - [c42]Saoni Banerji, Jordi Madrenas
Temperature and pressure characterization of the quality factor in a CMOS-MEMS resonator. IEEE SENSORS 2016: 1-3 - 2014
- [j12]Andrea De Marcellis
Quasi-digital front-ends for current measurement in integrated circuits with giant magnetoresistance technology. IET Circuits Devices Syst. 8(4): 291-300 (2014) - 2013
- [c41]Renhao Fan, Xiang Wang, Jordi Madrenas:
A Novel Alternative Exponent-Weighted Fuzzy C-Means Algorithm. GreenCom/iThings/CPScom 2013: 1767-1772 - [c40]Giovanny Sánchez
Spike-based analog-digital neuromorphic information processing system for sensor applications. ISCAS 2013: 1624-1627 - 2012
- [j11]Daniel Fernández
A Translinear, Log-Domain FPAA on Standard CMOS Technology. IEEE J. Solid State Circuits 47(2): 490-503 (2012) - [j10]Sergi Gorreta, Daniel Fernández
Pulsed Digital Oscillators for Electrostatic MEMS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2835-2845 (2012) - [c39]Piotr Michalik, Jordi Madrenas, Daniel Fernández
Sense/drive architecture for CMOS-MEMS accelerometers with relaxation oscillator and TDC. ICECS 2012: 937-940 - [c38]Jordi Madrenas, Daniel Fernández
LCMOS: Light-powered standard CMOS circuits. ISCAS 2012: 3029-3032 - 2011
- [j9]Daniel Fernández
A self-test and dynamics characterization circuit for MEMS electrostatic actuators. Microelectron. Reliab. 51(3): 602-609 (2011) - [c37]Jordi Madrenas, Daniel Fernández, Jordi Cosp, Juan Manuel Moreno, Luís Martínez-Alvarado, Giovanny Sánchez:
Bioinspired Sensory Integration for Environment-Perception Embedded Systems. BIODEVICES 2011: 260-267 - [c36]Eduard Alarcón, Daniel Fernández
Continuous-time CMOS adaptive asynchronous ΣΔ modulator approximating low-ƒs low-inband-error on-chip wideband power amplifier. ISCAS 2011: 301-304 - 2010
- [j8]Daniel Fernández
Experiments on the Release of CMOS-Micromachined Metal Layers. J. Sensors 2010: 937301:1-937301:7 (2010) - [c35]Jordi Madrenas, Daniel Fernández
A low-voltage current sorting circuit based on 4-T min-max CMOS switch. ICECS 2010: 351-354 - [c34]Giovanny Sánchez
Performance Evaluation and Scaling of a Multiprocessor Architecture Emulating Complex SNN Algorithms. ICES 2010: 145-156 - [c33]Kotaro Kobayashi, Juan Manuel Moreno, Jordi Madrenas
Implementation of a Power-Aware Dynamic Fault Tolerant Mechanism on the Ubichip Platform. ICES 2010: 299-309
2000 – 2009
- 2009
- [c32]Juan Manuel Moreno, Jordi Madrenas, Lukasz Kotynia:
Synchronous Digital Implementation of the AER Communication Scheme for Emulating Large-Scale Spiking Neural Networks Models. AHS 2009: 189-196 - [c31]Jordi Madrenas, Juan Manuel Moreno:
Strategies in SIMD Computing for Complex Neural Bioinspired Applications. AHS 2009: 376-381 - [c30]Juan Manuel Moreno, Jordi Madrenas:
A reconfigurable architecture for emulating large-scale bio-inspired systems. IEEE Congress on Evolutionary Computation 2009: 126-133 - [c29]Michael Hauptvogel, Jordi Madrenas, Juan Manuel Moreno:
SpiNDeK: An Integrated design tool for the multiprocessor emulation of complex bioinspired spiking neural networks. IEEE Congress on Evolutionary Computation 2009: 142-149 - [c28]Olivier Brousse, Jérémie Guillot, Thierry Gil, François Grize, Gilles Sassatelli, Juan Manuel Moreno, Jordi Madrenas, Alessandro E. P. Villa
JubiTool: Unified design flow for the Perplexus SIMD hardware accelerator. IEEE Congress on Evolutionary Computation 2009: 2070-2075 - [c27]Luís Martínez-Alvarado, Jordi Madrenas, Daniel Fernández
Translinear signal processing circuits in standard CMOS FPAA. ICECS 2009: 715-718 - [c26]Javier Soto Vargas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
Implementation of a Dynamic Fault-Tolerance Scaling Technique on a Self-Adaptive Hardware Architecture. ReConFig 2009: 445-450 - 2008
- [j7]Andres Upegui, Yann Thoma, Eduardo Sanchez, Andrés Pérez-Uribe, Juan Manuel Moreno, Jordi Madrenas, Gilles Sassatelli:
The PERPLEXUS bio-inspired hardware platform: A flexible and modular approach. Int. J. Knowl. Based Intell. Eng. Syst. 12(3): 201-212 (2008) - [j6]Daniel Fernández, Jordi Madrenas
A MOSFET-Based Wide-Dynamic-Range Translinear Element. IEEE Trans. Circuits Syst. II Express Briefs 55-II(11): 1124-1128 (2008) - [c25]Olivier Brousse, Gilles Sassatelli, Thierry Gil, Yoann Guillemenet, Michel Robert, François Grize, Eduardo Sanchez, Yann Thoma, Andres Upegui, Juan Manuel Moreno, Jordi Madrenas:
BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications. GEM 2008: 115-121 - [c24]Daniel Fernández, Jordi Madrenas, Piotr Michalik, Dominik Kapusta:
A reconfigurable translinear cell architecture for CMOS field-programmable analog arrays. ICECS 2008: 1034-1037 - [c23]Daniel Fernández, Jordi Madrenas
Position, damping and inertia control of parallel-plate electrostatic actuators. ISCAS 2008: 2118-2121 - [c22]Daniel Fernández, Jordi Madrenas
An asynchronous finite state machine controller for integrated buck-boost power converters in wideband signal-tracking applications. ISCAS 2008: 2210-2213 - [c21]Daniel Fernández, Jordi Madrenas
Exponential-enhanced characteristic of MOS transistors and its application to log-domain circuits. ISCAS 2008: 2334-2337 - [c20]Jordi Cosp
Implementation of compact VLSI FitzHugh-Nagumo neurons. ISCAS 2008: 2370-2373 - 2007
- [c19]Jose Antonio Casas, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
A Novel Hardware Architecture for Self-adaptive Systems. AHS 2007: 592-599 - [c18]Andres Upegui, Yann Thoma, Eduardo Sanchez, Andrés Pérez-Uribe, Juan Manuel Moreno, Jordi Madrenas:
The Perplexus bio-inspired reconfigurable circuit. AHS 2007: 600-605 - [i1]Alejandro Chinea Manrique De Lara, Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany:
Improving the Performance of PieceWise Linear Separation Incremental Algorithms for Practical Hardware Implementations. CoRR abs/0712.3654 (2007) - 2006
- [j5]Jordi Cosp
Design and basic blocks of a neuromorphic VLSI analogue vision system. Neurocomputing 69(16-18): 1962-1970 (2006) - 2005
- [c17]Jordi Madrenas
Selective similarity function for VLSI analog signal processing. ISCAS (4) 2005: 3926-3929 - [c16]Daniel Fernández
Mismatch-tolerant CMOS oscillator and excitatory synapse for bioinspired image segmentation. ISCAS (4) 2005: 4114-4117 - [c15]Gerard Villar, Eduard Alarcón, Jordi Madrenas
Energy optimization of tapered buffers for CMOS on-chip switching power converters. ISCAS (5) 2005: 4453-4456 - [e1]Juan Manuel Moreno, Jordi Madrenas, Jordi Cosp:
Evolvable Systems: From Biology to Hardware, 6th International Conference, ICES 2005, Sitges, Spain, September 12-14, 2005, Proceedings. Lecture Notes in Computer Science 3637, Springer 2005, ISBN 3-540-28736-1 [contents] - 2004
- [j4]Jordi Cosp
Synchronization of nonlinear electronic oscillators for neural computation. IEEE Trans. Neural Networks 15(5): 1315-1327 (2004) - [c14]Jordi Madrenas, Jordi Cosp, Lucas Oscar, Eduard Alarcón, Eva Vidal, Gerard Villar:
BIOSEG: a bioinspired vlsi analog system for image segmentation. ESANN 2004: 411-416 - 2003
- [j3]Jordi Cosp
Scene segmentation using neuromorphic oscillatory networks. IEEE Trans. Neural Networks 14(5): 1278-1296 (2003) - 2001
- [c13]Jordi Cosp, Jordi Madrenas:
A microelectronic implementation of a bioinspired analog matrix for object segmentation of a visual scene. ESANN 2001: 69-74 - 2000
- [c12]Jordi Madrenas
Mixed-signal VLSI for neural and fuzzy sequential processors. ISCAS 2000: 389-392
1990 – 1999
- 1999
- [c11]Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany
Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration. Evolvable Hardware 1999: 182-187 - 1998
- [c10]Juan Manuel Moreno, Jordi Madrenas
Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices. ICES 1998: 345-355 - 1997
- [c9]Juan Manuel Moreno, Jordi Madrenas
Analog Sequential Architecture for Neuro-Fuzzy Models VLSI Implementation. ICANN 1997: 1199-1204 - [c8]Juan Manuel Moreno, Jordi Madrenas, Joan Cabestany, J. R. Laúna:
Practical Design Methodology for Commercial Automatic Coin Recognizers Based on Neural Decision Engines. ICONIP (1) 1997: 662-665 - [c7]Alejandro Chinea Manrique De Lara, Juan Manuel Moreno, Jordi Madrenas
Improving the Performance of Piecewise Linear Separation Incremental Algorithms for Practical Hardware Implementations. IWANN 1997: 607-616 - [c6]Jordi Madrenas
Synthesis and Optimization of a Bit-Serial Pipeline Kernel Processor. IWANN 1997: 801-810 - [c5]Juan Manuel Moreno, Jordi Madrenas
Using Classical and Evolutive Neural Models in Industrial Applications: A Case Study for an Automatic Coin Classifier. IWANN 1997: 922-931 - 1995
- [c4]Josep Cugueró, Jordi Madrenas, Juan Manuel Moreno, Joan Cabestany:
Derivation of a new criterion function based on an information measure for improving piecewise linear separation incremental algorithms. ESANN 1995 - [c3]Juan Manuel Moreno, F. X. Vazquez, Francisco Castillo, Jordi Madrenas, Joan Cabestany:
A deterministic method for establishing the initial conditions in the RCE algorithm. ESANN 1995 - [c2]Philippe Thissen, Michel Verleysen, Jean-Didier Legat, Jordi Madrenas
A VLSI System for Neural Bayesian and LVQ Classification. IWANN 1995: 696-703 - [c1]Juan Manuel Moreno, Jordi Madrenas
Digital Hardware Implementation of ROI Incremental Algorithms. IWANN 1995: 761-770 - 1994
- [j2]Michel Verleysen, Philippe Thissen, Jean-Luc Voz, Jordi Madrenas
An analog processor architecture for a neural network classifier. IEEE Micro 14(3): 16-28 (1994) - [j1]Juan Manuel Moreno, Francisco Castillo, Joan Cabestany
An analog systolic neural processing architecture. IEEE Micro 14(3): 51-59 (1994)
Coauthor Index
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