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Trailokya Nath Sasamal
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2020 – today
- 2024
- [j8]Vineet Jaiswal
, Trailokya Nath Sasamal:
Placement and routing approach for MQCA-based designs with BFS and A* algorithms. Comput. Electr. Eng. 120: 109771 (2024) - 2023
- [j7]Vineet Jaiswal
, Trailokya Nath Sasamal:
A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata. IEEE Embed. Syst. Lett. 15(3): 133-136 (2023) - [j6]Vineet Jaiswal
, Trailokya Nath Sasamal:
Novel approach for the design of efficient full adder in MQCA. J. Supercomput. 79(7): 7900-7915 (2023) - 2022
- [j5]Ashutosh Kumar Singh, Trailokya Nath Sasamal, Lau Siong Hoe, P. W. Chandana Prasad
, Saeed Rasouli Heikalabad:
Guest editorial: Introduction to the special section on recent advances and challenges in quantum-dot cellular automata (VSI-QCA). Comput. Electr. Eng. 102: 108247 (2022) - [c2]Trailokya Nath Sasamal, Gaurav Saini, Vineet Jaiswal
:
High Speed Comparator and Parity generator in QCA based on optimal XOR structure. RTSI 2022: 13-18 - 2020
- [b1]Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan:
Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective. Studies in Computational Intelligence 879, Springer 2020, ISBN 978-981-15-1822-5, pp. 1-148
2010 – 2019
- 2019
- [j4]Trailokya Nath Sasamal
, Ashutosh Kumar Singh
, Umesh Ghanekar
:
Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates. J. Circuits Syst. Comput. 28(5): 1950079:1-1950079:20 (2019) - 2018
- [j3]Ashvin Chudasama, Trailokya Nath Sasamal, Jyoti Yadav:
An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata. Comput. Electr. Eng. 65: 527-542 (2018) - [j2]Trailokya Nath Sasamal, Ashutosh Kumar Singh
, Umesh Ghanekar
:
Efficient design of coplanar ripple carry adder in QCA. IET Circuits Devices Syst. 12(5): 594-605 (2018) - [j1]Trailokya Nath Sasamal
, Anand Mohan, Ashutosh Kumar Singh
:
Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata. J. Circuits Syst. Comput. 27(2): 1850021:1-1850021:19 (2018) - 2017
- [c1]Ramanand Jaiswal, Trailokya Nath Sasamal:
Efficient design of full adder and subtractor using 5-input majority gate in QCA. IC3 2017: 1-6
Coauthor Index
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last updated on 2024-11-07 20:31 CET by the dblp team
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