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Thorben Moos
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2020 – today
- 2024
- [j15]Gaëtan Cassiers, Loïc Masure
, Charles Momin, Thorben Moos
Randomness Generation for Secure Hardware Masking - Unrolled Trivium to the Rescue. IACR Commun. Cryptol. 1(2): 4 (2024) - [j14]Bijan Fadaeinia
Static Leakage in Dual-Rail Precharge Logics. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(4): 509-540 (2024) - [j13]Thorben Moos, Sayandeep Saha, François-Xavier Standaert:
Prime Masking vs. Faults - Exponential Security Amplification against Selected Classes of Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2024(4): 690-736 (2024) - [c10]Lorenzo Grassi, Loïc Masure, Pierrick Méaux, Thorben Moos
Generalized Feistel Ciphers for Efficient Prime Field Masking. EUROCRYPT (3) 2024: 188-220 - [i18]Thorben Moos, Sayandeep Saha, François-Xavier Standaert:
Prime Masking vs. Faults - Exponential Security Amplification against Selected Classes of Attacks. IACR Cryptol. ePrint Arch. 2024: 147 (2024) - [i17]Lorenzo Grassi, Loïc Masure, Pierrick Méaux, Thorben Moos, François-Xavier Standaert:
Generalized Feistel Ciphers for Efficient Prime Field Masking - Full Version. IACR Cryptol. ePrint Arch. 2024: 431 (2024) - 2023
- [j12]Gaëtan Cassiers, Loïc Masure, Charles Momin, Thorben Moos
Prime-Field Masking in Hardware and its Soundness against Low-Noise SCA Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2023(2): 482-518 (2023) - [c9]Jakob Feldtkeller
Combined Private Circuits - Combined Security Refurbished. CCS 2023: 990-1004 - [c8]Aein Rezaei Shahmirzadi
Energy Consumption of Protected Cryptographic Hardware Cores - An Experimental Study. COSADE 2023: 195-220 - [c7]Loïc Masure
Effective and Efficient Masking with Low Noise Using Small-Mersenne-Prime Ciphers. EUROCRYPT (4) 2023: 596-627 - [c6]Endres Puschner, Thorben Moos, Steffen Becker
Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations. SP 2023: 56-74 - [i16]Gaëtan Cassiers, Loïc Masure, Charles Momin, Thorben Moos, Amir Moradi, François-Xavier Standaert:
Randomness Generation for Secure Hardware Masking - Unrolled Trivium to the Rescue. IACR Cryptol. ePrint Arch. 2023: 1134 (2023) - [i15]Jakob Feldtkeller, Tim Güneysu, Thorben Moos, Jan Richter-Brockmann, Sayandeep Saha, Pascal Sasdrich, François-Xavier Standaert:
Combined Private Circuits - Combined Security Refurbished. IACR Cryptol. ePrint Arch. 2023: 1341 (2023) - 2022
- [b1]Thorben Moos:
Physical security for next generation CMOS ICs. Ruhr University Bochum, Germany, 2022 - [j11]Timo Bartkewitz, Sven Bettendorf, Thorben Moos
Beware of Insufficient Redundancy An Experimental Evaluation of Code-based FI Countermeasures. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(3): 438-462 (2022) - [i14]Loïc Masure, Pierrick Méaux, Thorben Moos, François-Xavier Standaert:
Effective and Efficient Masking with Low Noise using Small-Mersenne-Prime Ciphers. IACR Cryptol. ePrint Arch. 2022: 863 (2022) - [i13]Endres Puschner, Thorben Moos, Steffen Becker
Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations. IACR Cryptol. ePrint Arch. 2022: 1720 (2022) - 2021
- [j10]Oleksiy Lisovets
Let's Take it Offline: Boosting Brute-Force Attacks on iPhone's User Authentication through SCA. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 496-519 (2021) - [j9]Thorben Moos
DL-LA: Deep Learning Leakage Assessment A modern roadmap for SCA evaluations. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 552-598 (2021) - [j8]Thorben Moos
Countermeasures against Static Power Attacks - Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS -. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 780-805 (2021) - [j7]Gregor Leander
The SPEEDY Family of Block Ciphers Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(4): 510-545 (2021) - [c5]Nicolai Müller
Low-Latency Hardware Masking of PRINCE. COSADE 2021: 148-167 - [i12]Oleksiy Lisovets, David Knichel, Thorben Moos, Amir Moradi:
Let's Take it Offline: Boosting Brute-Force Attacks on iPhone's User Authentication through SCA. IACR Cryptol. ePrint Arch. 2021: 460 (2021) - [i11]Nicolai Müller, Thorben Moos, Amir Moradi:
Low-Latency Hardware Masking of PRINCE. IACR Cryptol. ePrint Arch. 2021: 868 (2021) - [i10]Gregor Leander, Thorben Moos, Amir Moradi, Shahram Rasoolzadeh:
The SPEEDY Family of Block Ciphers - Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures. IACR Cryptol. ePrint Arch. 2021: 960 (2021) - 2020
- [j6]Thorben Moos:
Unrolled Cryptography on Silicon A Physical Security Analysis. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2020(4): 416-442 (2020) - [j5]Thorben Moos
Static Power Side-Channel Analysis - An Investigation of Measurement Factors. IEEE Trans. Very Large Scale Integr. Syst. 28(2): 376-389 (2020) - [j4]Samaneh Ghandali, Thorben Moos
Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1435-1448 (2020) - [c4]David Knichel, Thorben Moos
The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs. ETS 2020: 1-6 - [c3]Dusan Bozilov, Maria Eichlseder
PRINCEv2 - More Security for (Almost) No Overhead. SAC 2020: 483-511 - [i9]David Knichel, Thorben Moos, Amir Moradi:
The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs. IACR Cryptol. ePrint Arch. 2020: 369 (2020) - [i8]Bijan Fadaeinia, Thorben Moos, Amir Moradi:
BSPL: Balanced Static Power Logic. IACR Cryptol. ePrint Arch. 2020: 558 (2020) - [i7]Dusan Bozilov, Maria Eichlseder, Miroslav Knezevic, Baptiste Lambin, Gregor Leander, Thorben Moos, Ventzislav Nikov, Shahram Rasoolzadeh, Yosuke Todo, Friedrich Wiemer:
PRINCEv2 - More Security for (Almost) No Overhead. IACR Cryptol. ePrint Arch. 2020: 1269 (2020)
2010 – 2019
- 2019
- [j3]Thorben Moos
Glitch-Resistant Masking Revisited or Why Proofs in the Robust Probing Model are Needed. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(2): 256-292 (2019) - [j2]Thorben Moos:
Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(3): 202-232 (2019) - [j1]Naghmeh Karimi, Thorben Moos, Amir Moradi
Exploring the Effect of Device Aging on Static Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(3): 233-256 (2019) - [i6]Samaneh Ghandali, Thorben Moos, Amir Moradi, Christof Paar:
Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations. CoRR abs/1910.00737 (2019) - [i5]Felix Wegener, Thorben Moos, Amir Moradi:
DL-LA: Deep Learning Leakage Assessment: A modern roadmap for SCA evaluations. IACR Cryptol. ePrint Arch. 2019: 505 (2019) - 2018
- [i4]Thorben Moos, Amir Moradi, Tobias Schneider, François-Xavier Standaert:
Glitch-Resistant Masking Revisited - or Why Proofs in the Robust Probing Model are Needed. IACR Cryptol. ePrint Arch. 2018: 490 (2018) - [i3]Thorben Moos, Amir Moradi, Bastian Richter:
Static Power Side-Channel Analysis - A Survey on Measurement Factors. IACR Cryptol. ePrint Arch. 2018: 676 (2018) - 2017
- [c2]Thorben Moos
On the Easiness of Turning Higher-Order Leakages into First-Order. COSADE 2017: 153-170 - [c1]Thorben Moos
Static power side-channel analysis of a threshold implementation prototype chip. DATE 2017: 1324-1329 - [i2]Thorben Moos, Amir Moradi:
On the Easiness of Turning Higher-Order Leakages into First-Order. IACR Cryptol. ePrint Arch. 2017: 283 (2017) - 2016
- [i1]Thorben Moos, Amir Moradi, Bastian Richter:
Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip. IACR Cryptol. ePrint Arch. 2016: 1135 (2016)
Coauthor Index
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last updated on 2024-12-10 20:47 CET by the dblp team
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