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Mohammad Shihabul Haque
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2020 – today
- 2020
- [i5]Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran, Karthik Thangamariappan:
Contract-based Hierarchical Resilience Management for Cyber-Physical Systems. CoRR abs/2004.04441 (2020)
2010 – 2019
- 2018
- [j2]Mohammad Shihabul Haque, Daniel Jun Xian Ng, Arvind Easwaran
, Karthikeyan Thangamariappan:
Contract-Based Hierarchical Resilience Management for Cyber-Physical Systems. Computer 51(11): 56-65 (2018) - [j1]Mohammad Shihabul Haque
Predictability and Performance Aware Replacement Policy PVISAM for Unified Shared Caches in Real-time Multicores. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2720-2731 (2018) - [c9]Mohammad Shihabul Haque, Sriram Vasudevan, Alamuri Sriram Nihar, Arvind Easwaran
A Self-Reconfiguring Cache Architecture to Improve Control Quality in Cyber-Physical Systems. ISORC 2018: 116-123 - 2015
- [c8]Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei:
Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems. ASP-DAC 2015: 435-440 - [i4]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran:
DEW: A Fast Level 1 Cache Simulation Approach for Embedded Processors with FIFO Replacement Policy. CoRR abs/1506.03181 (2015) - [i3]Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, Qiang Wu, Shaobo Luo:
TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs. CoRR abs/1506.03182 (2015) - [i2]Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran:
CIPARSim: Cache Intersection Property Assisted Rapid Single-pass FIFO Cache Simulation Technique. CoRR abs/1506.03186 (2015) - [i1]Mohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei:
Accelerating Non-volatile/Hybrid Processor Cache Design Space Exploration for Application Specific Embedded Systems. CoRR abs/1506.03193 (2015) - 2013
- [c7]Mohammad Shihabul Haque, Akash Kumar
TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs. ASP-DAC 2013: 320-325 - 2012
- [c6]Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS 2012: 151-160 - 2011
- [c5]Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. ICCAD 2011: 126-133 - 2010
- [c4]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. DAC 2010: 356-361 - [c3]Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran:
Rapid runtime estimation methods for pipelined MPSoCs. DATE 2010: 363-368 - [c2]Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. DATE 2010: 496-501
2000 – 2009
- 2009
- [c1]Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. CODES+ISSS 2009: 295-304
Coauthor Index
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