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Weizhe Hua
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2020 – today
- 2024
- [c14]Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh:
Information Flow Control in Machine Learning through Modular Model Architecture. USENIX Security Symposium 2024 - 2023
- [i11]Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh:
Information Flow Control in Machine Learning through Modular Model Architecture. CoRR abs/2306.03235 (2023) - 2022
- [j2]Weizhe Hua
, Zhiru Zhang
Reverse-Engineering CNN Models Using Side-Channel Attacks. IEEE Des. Test 39(4): 15-22 (2022) - [c13]Weizhe Hua, Muhammad Umar
GuardNN: secure accelerator architecture for privacy-preserving deep learning. DAC 2022: 349-354 - [c12]Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le:
Transformer Quality in Linear Time. ICML 2022: 9099-9117 - [c11]Muhammad Umar
SoftVN: efficient memory protection via software-provided version numbers. ISCA 2022: 160-172 - [c10]Weizhe Hua, Muhammad Umar
MGX: near-zero overhead memory protection for data-intensive accelerators. ISCA 2022: 726-741 - [i10]Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le:
Transformer Quality in Linear Time. CoRR abs/2202.10447 (2022) - [i9]Yaohui Cai, Weizhe Hua, Hongzheng Chen
Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR abs/2203.02549 (2022) - 2021
- [c9]Yanqi Zhang
Sinan: ML-based and QoS-aware resource management for cloud microservices. ASPLOS 2021: 167-181 - [c8]Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh:
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. NeurIPS 2021: 18527-18538 - [i8]Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou:
Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices. CoRR abs/2105.13424 (2021) - [i7]Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh:
BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. CoRR abs/2109.14707 (2021) - [i6]Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou:
Sinan: Data Driven Resource Management for Cloud Microservices. CoRR abs/2112.06254 (2021) - 2020
- [c7]Yichi Zhang
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. ICLR 2020 - [i5]Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang:
Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. CoRR abs/2002.07136 (2020) - [i4]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. CoRR abs/2004.09679 (2020) - [i3]Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. CoRR abs/2008.11632 (2020) - [i2]Qiwei Yuan, Weizhe Hua, Yi Zhou, Cunxi Yu:
Contrastive Weight Regularization for Large Minibatch SGD. CoRR abs/2011.08968 (2020)
2010 – 2019
- 2019
- [c6]Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang
Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. MICRO 2019: 139-150 - [c5]Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Channel Gating Neural Networks. NeurIPS 2019: 1884-1894 - 2018
- [c4]Weizhe Hua, Zhiru Zhang
Reverse engineering convolutional neural networks through side-channel information leaks. DAC 2018: 4:1-4:6 - [i1]Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh:
Channel Gating Neural Networks. CoRR abs/1805.12549 (2018) - 2017
- [c3]Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh
Secure Information Flow Verification with Mutable Dependent Types. DAC 2017: 6:1-6:6 - 2016
- [j1]Ramy N. Tadros
A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs 63-II(9): 858-862 (2016) - [c2]Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans
Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC 2016: 11-18 - [c1]Weizhe Hua, Ramy N. Tadros, Peter A. Beerel:
Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures. ISLPED 2016: 16-21
Coauthor Index
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