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2020 – today
- 2024
- [j18]Yukai Ping
, He Jiang
Latency-Based Inter-Operator Scheduling for CNN Inference Acceleration on GPU. IEEE Trans. Serv. Comput. 17(1): 277-290 (2024) - [j17]He Jiang
A Testing Program and Pragma Combination Selection Based Framework for High-Level Synthesis Tool Pragma-Related Bug Detection. IEEE Trans. Software Eng. 50(4): 937-955 (2024) - [j16]Haoxin Tu
Isolating Compiler Bugs by Generating Effective Witness Programs With Large Language Models. IEEE Trans. Software Eng. 50(7): 1768-1788 (2024) - [j15]Xin Chen, Tian Sun, Dongling Zhuang, Dongjin Yu, He Jiang, Zhide Zhou, Sicheng Li:
HetFL: Heterogeneous Graph-Based Software Fault Localization. IEEE Trans. Software Eng. 50(11): 2884-2905 (2024) - 2023
- [j14]Haoxin Tu
Detecting C++ Compiler Front-End Bugs via Grammar Mutation and Differential Testing. IEEE Trans. Reliab. 72(1): 343-357 (2023) - [c8]Yue Wang, Zhide Zhou, Zhilei Ren, Dong Liu, He Jiang:
A Comprehensive Study of WebAssembly Runtime Bugs. SANER 2023: 355-366 - [c7]Le Chen, Zhide Zhou, Xiaochen Li, He Jiang:
Detecting JavaScript Transpiler Bugs with Grammar-guided Mutation. SANER 2023: 558-568 - [i1]Haoxin Tu, Zhide Zhou, He Jiang, Imam Nur Bani Yusuf, Yuxian Li, Lingxiao Jiang:
LLM4CBI: Taming LLMs to Generate Effective Test Programs for Compiler Bug Isolation. CoRR abs/2307.00593 (2023) - 2022
- [j13]Yixuan Tang, Zhilei Ren
Detecting Compiler Bugs Via a Deep Learning-Based Framework. Int. J. Softw. Eng. Knowl. Eng. 32(5): 661-691 (2022) - [j12]He Jiang
SMARTEST: A Surrogate-Assisted Memetic Algorithm for Code Size Reduction. IEEE Trans. Reliab. 71(1): 190-203 (2022) - [j11]Zhide Zhou
LocSeq: Automated Localization for Compiler Optimization Sequence Bugs of LLVM. IEEE Trans. Reliab. 71(2): 896-910 (2022) - [j10]He Jiang
CTOS: Compiler Testing for Optimization Sequences of LLVM. IEEE Trans. Software Eng. 48(7): 2339-2358 (2022) - [j9]Yixuan Tang
Detecting Compiler Warning Defects Via Diversity-Guided Program Mutation. IEEE Trans. Software Eng. 48(11): 4411-4432 (2022) - [c6]Zhilei Ren, Shiwei Sun, Jifeng Xuan, Xiaochen Li, Zhide Zhou, He Jiang:
Automated Patching for Unreproducible Builds. ICSE 2022: 200-211 - [c5]Haoxin Tu, He Jiang, Xiaochen Li, Zhilei Ren, Zhide Zhou, Lingxiao Jiang
Remgen: Remanufacturing a Random Program Generator for Compiler Testing. ISSRE 2022: 529-540 - [c4]Shikai Guo, He Jiang, Zhihao Xu, Xiaochen Li, Zhilei Ren, Zhide Zhou, Rong Chen:
Detecting Simulink compiler bugs via controllable zombie blocks mutation. ESEC/SIGSOFT FSE 2022: 1061-1072 - 2021
- [j8]Junyan Qian
An improved algorithm for accelerating reconfiguration of VLSI array. Integr. 79: 124-132 (2021) - [j7]Zhide Zhou, Zhilei Ren, Guojun Gao
An empirical study of optimization bugs in GCC and LLVM. J. Syst. Softw. 174: 110884 (2021) - [c3]Zhilei Ren, Xiaofei Fan, Xiaochen Li, Zhide Zhou, He Jiang:
Multi-objective Evolutionary Algorithm for String SMT Solver Testing. DSA 2021: 102-113 - 2020
- [j6]Junyan Qian, Bisheng Huang, Hao Ding
An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray. Integr. 75: 63-72 (2020) - [j5]Junyan Qian
Efficient Reconfiguration Algorithm With Flexible Rerouting Schemes for Constructing 3-D VLSI Subarrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 267-271 (2020) - [c2]Hao Chen, Zhilei Ren, Lei Qiao, Zhide Zhou, Guojun Gao, Yue Ma, He Jiang:
AdaBoost-based Refused Bequest Code Smell Detection with Synthetic Instances. DSA 2020: 78-89
2010 – 2019
- 2017
- [j4]Junyan Qian
A Mathematical Model for Reconfiguring VLSI Subarrays Under Row and Column Rerouting. IEEE Access 5: 23912-23919 (2017) - 2016
- [j3]Junyan Qian, Zhide Zhou, Lingzhong Zhao, Tianlong Gu, Liang Chang:
An integer programming method for constructing tightly coupled VLSI subarrays. IEICE Electron. Express 13(11): 20160359 (2016) - [j2]Junyan Qian, Wei Cao, Jia Hu, Jingwei Zhang, Zhoubo Xu, Zhide Zhou:
Satisfiability-based method for reconfiguring power efficient VLSI array. IEICE Electron. Express 13(23): 20160930 (2016) - [j1]Junyan Qian
Optimal Reconfiguration of High-Performance VLSI Subarrays with Network Flow. IEEE Trans. Parallel Distributed Syst. 27(12): 3575-3587 (2016) - [c1]Junyan Qian, Zhide Zhou, Lingzhong Zhao, Tianlong Gu:
An Improved Reconfiguration Algorithm for VLSI Arrays with A-Star. ICCSA (2) 2016: 331-343
Coauthor Index
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last updated on 2024-12-12 20:59 CET by the dblp team
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