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Bangan Liu
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2020 – today
- 2024
- [j17]Yuncheng Zhang
, Zheng Sun
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. IEEE J. Solid State Circuits 59(4): 993-1005 (2024) - [c21]Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. ISSCC 2024: 192-194 - 2023
- [c20]Dingxin Xu, Yuncheng Zhang, Hongye Huang
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. CICC 2023: 1-2 - [c19]Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. ISSCC 2023: 80-81 - [c18]Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j16]Junjun Qiu, Bangan Liu, Yuncheng Zhang, Atsushi Shirane, Kenichi Okada:
A low-power digital baseband circuit for GMSK demodulation in sub-GHz application. IEICE Electron. Express 19(12): 20220201 (2022) - [j15]Yuncheng Zhang, Bangan Liu, Teruki Someya, Rui Wu, Junjun Qiu, Atsushi Shirane, Kenichi Okada:
A 0.37mm2 Fully-Integrated Wide Dynamic Range Sub-GHz Receiver Front-End without Off-Chip Matching Components. IEICE Trans. Electron. 105-C(7): 334-342 (2022) - [j14]Yun Wang
A Ka-Band SATCOM Transceiver in 65-nm CMOS With High-Linearity TX and Dual-Channel Wide-Dynamic-Range RX for Terrestrial Terminal. IEEE J. Solid State Circuits 57(2): 356-370 (2022) - 2021
- [j13]Jian Pang
A CMOS Dual-Polarized Phased-Array Beamformer Utilizing Cross-Polarization Leakage Cancellation for 5G MIMO Systems. IEEE J. Solid State Circuits 56(4): 1310-1326 (2021) - [j12]Junjun Qiu
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits 56(12): 3741-3755 (2021) - [j11]Bangan Liu
A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 603-616 (2021) - [c17]Yuncheng Zhang
A DSM-based Polar Transmitter with 23.8% System Efficiency. ASP-DAC 2021: 1-2 - [c16]Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. ESSCIRC 2021: 499-502 - [c15]Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. ISSCC 2021: 454-456 - 2020
- [j10]Zheng Sun, Dingxin Xu, Hongye Huang
A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. IEICE Trans. Electron. 103-C(10): 505-513 (2020) - [j9]Yun Wang
A 39-GHz 64-Element Phased-Array Transceiver With Built-In Phase and Amplitude Calibrations for Large-Array 5G NR in 65-nm CMOS. IEEE J. Solid State Circuits 55(5): 1249-1269 (2020) - [j8]Jian Pang
A 28-GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. IEEE J. Solid State Circuits 55(9): 2371-2386 (2020) - [c14]Zheng Li, Jian Pang, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You
A 28GHz CMOS Differential Bi-Directional Amplifier for 5G NR. ASP-DAC 2020: 5-6 - [c13]Jian Pang, Zheng Li, Xueting Luo, Joshua Alvin, Rattanan Saengchan, Ashbir Aviat Fadila, Kiyoshi Yanagisawa, Yi Zhang
A 28-GHz CMOS Phased-Array Beamformer Supporting Dual-Polarized MIMO with Cross-Polarization Leakage Cancellation. VLSI Circuits 2020: 1-2 - [c12]Yuncheng Zhang
A 29% PAE 1.5Bit-DSM-Based Polar Transmitter with Spur-Mitigated Injection-Locked PLL. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j7]Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Rui Wu, Atsushi Shirane
A Power-Efficient Pulse-VCO for Chip-Scale Atomic Clock. IEICE Trans. Electron. 102-C(4): 276-286 (2019) - [j6]Jian Pang
A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio. IEEE J. Solid State Circuits 54(5): 1228-1242 (2019) - [j5]Yun Wang
A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. IEEE J. Solid State Circuits 54(5): 1363-1374 (2019) - [j4]Jian Pang
A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance. IEEE J. Solid State Circuits 54(5): 1375-1390 (2019) - [c11]Bangan Liu, Yuncheng Zhang
An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC 2019: 1-4 - [c10]Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO. ESSCIRC 2019: 101-104 - [c9]Jian Pang, Zheng Li, Ryo Kubozoe, Xueting Luo, Rui Wu, Yun Wang, Dongwon You
A 28GHz CMOS Phased-Array Beamformer Utilizing Neutralized Bi-Directional Technique Supporting Dual-Polarized MIMO for 5G NR. ISSCC 2019: 344-346 - [c8]Haosheng Zhang, Aravind Tharayil Narayanan, Hans Herdian, Bangan Liu, Yun Wang, Atsushi Shirane, Kenichi Okada
0.2mW 70Fsrms-Jitter Injection-Locked PLL Using De-Sensitized SSPD-Based Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference Spur. VLSI Circuits 2019: 38- - 2018
- [j3]Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan
A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. IEICE Trans. Electron. 101-C(2): 126-134 (2018) - [c7]Jian Pang, Korkut Kaan Tokgoz
A 28.16-Gb/s Area-Efficient 60GHz CMOS Bi-Directional Transceiver for IEEE 802.11ay. A-SSCC 2018: 77-78 - [c6]Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang
A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC 2018: 1-4 - 2017
- [j2]Rui Wu
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52(11): 2871-2891 (2017) - [c5]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON 2017: 1025-1028 - [c4]Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan
An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC 2017: 13-14 - [c3]Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon
24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC 2017: 424-425 - 2016
- [c2]Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon
An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC 2016: 197-200 - [c1]Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC 2016: 248-249 - 2015
- [j1]Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan
A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express 12(15): 20150531 (2015)
Coauthor Index
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