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Gianluca Giustolisi
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2020 – today
- 2024
- [c40]Minoo Eghtesadi, Gianluca Giustolisi
, Salvatore Pennisi, Egidio Ragonese:
A 28-nm CMOS 60-GHz LNA for OOK Low-Power Receivers. PRIME 2024: 1-4 - 2022
- [j26]Francesco Centurelli
A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs. IEEE Access 10: 25892-25900 (2022) - [j25]Gianluca Giustolisi
Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders. IEEE Access 10: 75482-75494 (2022) - [j24]Gianluca Giustolisi
A Novel Clock Gating Approach for the Design of Low-Power Linear Feedback Shift Registers. IEEE Access 10: 99702-99708 (2022) - [c39]Angelo Lucio Bella, Gianluca Giustolisi, Manuela La Rosa, Giovanni Sicurella:
Design Methodology of the Output Power Stage of a Step-Down DC-DC Converter. PRIME 2022: 261-264 - 2021
- [j23]Gianluca Giustolisi
Design of CMOS three-stage amplifiers for near-to-minimum settling-time. Microelectron. J. 107: 104939 (2021) - [j22]Gianluca Giustolisi
Design of Three-Stage OTA Based on Settling-Time Requirements Including Large and Small Signal Behavior. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 998-1011 (2021) - [c38]Gianluca Giustolisi, Gaetano Palumbo:
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints. ISCAS 2021: 1-5
2010 – 2019
- 2019
- [j21]Gianluca Giustolisi
Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies. Microelectron. J. 92 (2019) - [j20]Andrea Ballo
Optimized Charge Pump With Clock Booster for Reduced Rise Time or Silicon Area. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1977-1981 (2019) - [j19]Gianluca Giustolisi
In-Depth Analysis of Pole-Zero Compensations in CMOS Operational Transconductance Amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(12): 4557-4570 (2019) - 2018
- [j18]Gianluca Giustolisi
Bessel-like compensation of three-stage operational transconductance amplifiers. Int. J. Circuit Theory Appl. 46(4): 729-747 (2018) - [j17]Giulia Di Capua
Guest Editorial Special Issue on Selected Papers from PRIME 2017 and SMACD 2017. Integr. 63: 273-274 (2018) - [c37]Gianluca Giustolisi, Gaetano Palumbo:
Design of CMOS OTAs with Settling-Time Constraints. ICECS 2018: 505-508 - [c36]Andrea Ballo
A Clock Boosted Charge Pump with Reduced Rise Time. ICECS 2018: 605-608 - [c35]Gianluca Giustolisi
Non-Inverting Class-AB CMOS Output Stage for Driving High-Capacitive Loads. ISCAS 2018: 1-4 - [c34]Gianluca Giustolisi
Settling-time oriented OTA design through the approximation of the ideal delay. ISCAS 2018: 1-4 - 2017
- [j16]Gianluca Giustolisi
Robust design of CMOS amplifiers oriented to settling-time specification. Int. J. Circuit Theory Appl. 45(10): 1329-1348 (2017) - 2016
- [c33]Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro
Verilog-a modeling of Silicon Photo-Multipliers. ISCAS 2016: 1270-1273 - 2015
- [j15]Gianluca Giustolisi
Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(11): 2641-2651 (2015) - [j14]Gianluca Giustolisi
Integrated Quenching-and-Reset Circuit for Single-Photon Avalanche Diodes. IEEE Trans. Instrum. Meas. 64(1): 271-277 (2015) - 2014
- [c32]Gianluca Giustolisi, Alfio Dario Grasso
Monolithic quenching-and-reset circuit for single-photon avalanche diodes. ICECS 2014: 76-79 - 2013
- [c31]Gianluca Giustolisi, Gaetano Palumbo, Paolo Finocchiaro, Alfio Pappalardo:
A simple extraction procedure for determining the electrical parameters in Silicon Photomultipliers. ECCTD 2013: 1-4 - 2012
- [j13]Gianluca Giustolisi
Behavioral modeling of statistical phenomena of single-photon avalanche diodes. Int. J. Circuit Theory Appl. 40(7): 661-679 (2012) - [j12]Elio Consoli, Gianluca Giustolisi
An Accurate Ultra-Compact I-V Model for Nanometer MOS Transistors With Applications on Digital Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 159-169 (2012) - [j11]Gianluca Giustolisi
Robust Miller Compensation With Current Amplifiers Applied to LDO Voltage Regulators. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1880-1893 (2012) - [c30]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Logic gates dynamic modeling by means of an ultra-compact MOS model. ISCAS 2012: 3250-3253 - 2011
- [c29]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
Inverter transfer curves and SRAM noise margin evaluation based on an ultra-compact MOS model. ECCTD 2011: 512-515 - [c28]Elio Consoli, Gianluca Giustolisi, Gaetano Palumbo:
An ultra-compact MOS model in nanometer technologies. ECCTD 2011: 520-523 - [c27]Gianluca Giustolisi, Rosario Mita, Gaetano Palumbo:
Verilog-A modeling of SPAD statistical phenomena. ISCAS 2011: 773-776
2000 – 2009
- 2008
- [c26]David Cristaldi, Gianluca Giustolisi:
Modeling of EMI propagation in switched-capacitor ΣΔ A/D converter. ICECS 2008: 1241-1244 - [c25]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale:
Low-voltage LDO Compensation Strategy based on Current Amplifiers. ISCAS 2008: 2681-2684 - 2007
- [j10]Gianluca Giustolisi
High-Drive and Linear CMOS Class-AB Pseudo-Differential Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 54-II(2): 112-116 (2007) - [j9]Arnaldo D'Amico, Christian Falconi
Resistance of Feedback Amplifiers: A Novel Representation. IEEE Trans. Circuits Syst. II Express Briefs 54-II(4): 298-302 (2007) - [c24]Gianluca Giustolisi, Gaetano Palumbo, Ester Spitale:
LDO compensation strategy based on current buffer/amplifiers. ECCTD 2007: 116-119 - [c23]Gianluca Giustolisi:
Two-Stage OTA Design Based on Settling-Time Constraints. ISCAS 2007: 469-472 - [c22]Christian Falconi, Arnaldo D'Amico, Gianluca Giustolisi, Gaetano Palumbo:
Rosenstark-like Representation of Feedback Amplifier Resistance. ISCAS 2007: 2212-2215 - 2006
- [c21]Gianluca Giustolisi, Gaetano Palumbo, Christian Falconi
NMOS Low Drop-Out Regulator with Dynamic Biasing. ICECS 2006: 204-207 - [c20]Christian Falconi, Gianluca Giustolisi:
Analysis of power supply gain of CMOS bandgap references. ISCAS 2006 - 2005
- [j8]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Design and Comparison of Very Low-Voltage CMOS Output Stages. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(8): 1545-1556 (2005) - [c19]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Guidelines for designing class-AB output stages. ECCTD 2005: 109-112 - [c18]Gianluca Giustolisi, Gaetano Palumbo, Maurizio Gaibotti, Michelangelo Pisasale:
Statistical analysis of CMOS current reference. ECCTD 2005: 341-344 - [c17]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Analysis and optimization of a low-voltage class-AB output stage. ICECS 2005: 1-4 - [c16]Gianluca Giustolisi, Gaetano Palumbo:
Comparison of methods for predicting distortion in class-AB stages. ICECS 2005: 1-4 - 2004
- [j7]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Exploiting the high-frequency performance of low-voltage low-power SC filters. IEEE Trans. Circuits Syst. II Express Briefs 51-II(2): 77-84 (2004) - [c15]Gianluca Giustolisi, Gaetano Palumbo:
Sigma-Delta A/D fuzzy converter. ISCAS (4) 2004: 677-680 - 2003
- [j6]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Analysis, modelling and optimization of a gain boosted telescopic amplifier. Int. J. Circuit Theory Appl. 31(5): 513-528 (2003) - [j5]Gianluca Giustolisi, Gaetano Palumbo, M. Criscione, F. Cutri:
A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE J. Solid State Circuits 38(1): 151-154 (2003) - [c14]Gianluca Giustolisi, Gaetano Palumbo:
A novel 1-V class-AB transconductor for improving speed performance in SC applications. ISCAS (1) 2003: 153-156 - [c13]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
A 1-V CMOS output stage with high linearity. ISCAS (1) 2003: 225-228 - [c12]Gianluca Giustolisi, Gaetano Palumbo:
A new method for evaluating harmonic distortion in push-pull output stages. ISCAS (1) 2003: 233-236 - [c11]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Design of low-voltage low-power SC filters for high-frequency applications. ISCAS (1) 2003: 605-608 - [c10]Gianluca Giustolisi, Alessandro Rizzo:
CMOS implementation of an extended CNN cell to deal with complex dynamics. ISCAS (5) 2003: 761-764 - 2002
- [j4]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi
Current-mode A/D fuzzy converter. IEEE Trans. Fuzzy Syst. 10(4): 533-540 (2002) - [c9]Gianluca Giustolisi, Gaetano Palumbo, Salvatore Pennisi
Statistical analysis of the resolution in a current-mode ADC. ICECS 2002: 5-8 - [c8]Walter Aloisi, Gianluca Giustolisi, Gaetano Palumbo:
Analysis and optimization of gain-boosted telescopic amplifiers. ISCAS (1) 2002: 321-324 - [c7]Gianluca Giustolisi, Gaetano Palumbo:
Analysis of power supply noise attenuation in a PTAT current source. ISCAS (1) 2002: 561-564 - 2001
- [j3]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
Analysis and optimization of a novel CMOS multiplier. Int. J. Circuit Theory Appl. 29(3): 321-330 (2001) - [c6]M. Criscione, Gianluca Giustolisi, A. Lionetto, M. Muscarà, Gaetano Palumbo:
A fuzzy controller for step-up DC/DC converters. ICECS 2001: 977-980 - [c5]Gianluca Giustolisi, Gaetano Palumbo:
Detailed frequency analysis of power supply rejection in Brokaw bandgap. ISCAS (1) 2001: 731-734 - 2000
- [j2]Gianluca Giustolisi, Giuseppe Palmisano, T. Segreto:
1.2-V CMOS op-amp with a dynamically biased output stage. IEEE J. Solid State Circuits 35(4): 632-636 (2000) - [j1]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
CMRR frequency response of CMOS operational transconductance amplifiers. IEEE Trans. Instrum. Meas. 49(1): 137-143 (2000) - [c4]Gianluca Giustolisi, Giuseppe Palmisano, Salvatore Pennisi:
High-linear class AB transconductor for high-frequency applications. ISCAS 2000: 169-172 - [c3]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
A fuzzy membership function circuit in SC technique. ISCAS 2000: 393-396
1990 – 1999
- 1998
- [c2]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo, C. Strano:
A Novel 1.5-V Cmos Mixer. Great Lakes Symposium on VLSI 1998: 113-117 - [c1]Gianluca Giustolisi, Giuseppe Palmisano, Gaetano Palumbo:
A 1.5 V CMOS voltage multiplier. ICECS 1998: 313-316
Coauthor Index
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last updated on 2024-08-05 20:19 CEST by the dblp team
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