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Po-Chang Wu
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2020 – today
- 2024
- [j5]Mahesh Kumar Chaubey
, Chih-Cheng Lin, Yin-Cheng Chang
A 0.01-to-2.6-GHz Two-Fold Current Reuse Dual Noise-Canceling LNA Achieving 6.8-K Noise Temperature for Quantum Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2504-2508 (2024) - 2020
- [j4]Chih-Yuan Yeh, Jung-Tang Huang, Sheng-Hsiang Tseng, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang:
A Low-Power Low-Noise Monolithic Accelerometer with Automatic Sensor Offset Calibration. Microelectron. J. 105: 104910 (2020) - [c10]Tzu-Wei Wang, Po-Chang Wu, Mark Po-Hung Lin
Late Breaking Results: Automatic Adaptive MOM Capacitor Cell Generation for Analog and Mixed-Signal Layout Design. DAC 2020: 1-2
2010 – 2019
- 2019
- [j3]Chih-Yuan Yeh, Jung-Tang Huang, Sheng-Hsiang Tseng, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang:
A low-power monolithic three-axis accelerometer with automatically sensor offset compensated and interface circuit. Microelectron. J. 86: 150-160 (2019) - [c9]Kuei-Cheng Lin, Po-Chang Wu, Yu-Chen Liu, Hann-Huei Tsai, Ying-Zong Juang:
A 2.5D mm-size Wafer-level CMOS-IPD Wireless Power Transfer Receiver Using Cross-coupled and Self-biasing Topology for Implantable Biomedical System. APCCAS 2019: 69-72 - [c8]Yu-Chen Liu, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang:
A Low-Cost 70Mbps Optical Detector Design For Optocoupler Application. APCCAS 2019: 269-272 - 2017
- [j2]Che-Lun Hung, Chun-Yuan Lin, Po-Chang Wu:
An Efficient GPU-Based Multiple Pattern Matching Algorithm for Packet Filtering. J. Signal Process. Syst. 86(2-3): 347-358 (2017) - 2016
- [j1]Po-Chang Wu, Hsuan-Tsung Hsu, Hsin-Li Chen, Wei Lee
Dielectric characterization and voltage holding ratio of blue-phase cells. Displays 44: 66-72 (2016) - [c7]Po-Chang Wu, Chih-Yuan Yeh, Hann-Huei Tsai, Ying-Zong Juang:
Low-frequency noise reduction technique for accelerometer readout circuit. APCCAS 2016: 483-486 - [c6]Chih-Yuan Yeh, Jung-Tang Huang, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang:
A low power and low noise CMOS chopper amplifier for use in capacitive type accelerometer. APCCAS 2016: 642-645 - 2015
- [c5]Che-Lun Hung, Po-Chang Wu, Hsiao-Hsi Wang, Chun-Yuan Lin:
Efficient Parallel Muti-pattern Matching Using GPGPU Acceleration for Packet Filtering. HPCC/CSS/ICESS 2015: 1843-1847 - [c4]Po-Chang Wu, Bin-Da Liu, Chih-Yuan Yeh, Sheng-Hsiang Tseng, Hann-Huei Tsai, Ying-Zong Juang:
Design of a 0.6-V 0.2-mW CMOS MEMS accelerometer. ICCE-TW 2015: 444-445 - 2014
- [c3]Kuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Hann-Huei Tsai, Ying-Zong Juang:
5-GHz SiGe linearity power amplifier using integrated feedforward architecture for WLAN applications. ISCAS 2014: 1508-1511 - 2013
- [c2]Po-Chang Wu, Bin-Da Liu, Yu-Chen Teng, Chih-Yuan Yeh, Sheng-Hsiang Tseng, Hann-Huei Tsai, Ying-Zong Juang:
Novel automatic offset cancellation approach for capacitive CMOS MEMS accelerometers. ISCE 2013: 147-148 - 2012
- [c1]Kuei-Cheng Lin, Hwann-Kaeo Chiou, Po-Chang Wu, Chu-Jung Sha, Chun-Lin Ko, Da-Chiang Chang, Ying-Zong Juang:
Variable gain active predistorter with linearity enhancement for a 2.4 GHz SiGe HBT power amplifier design. VLSI-DAT 2012: 1-4
Coauthor Index
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