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Câncio Monteiro
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2020 – today
- 2021
- [j3]Câncio Monteiro, Yasuhiro Takahashi:
Ultra-Low-Power FinFETs-Based TPCA-PUF Circuit for Secure IoT Devices. Sensors 21(24): 8302 (2021)
2010 – 2019
- 2018
- [c8]Câncio Monteiro, Apolinario Maria, Yasuhiro Takahashi:
Low Power Source Biased Semi-Adiabatic Logic Circuit for IoT Devices. ISPACS 2018: 43-47 - 2015
- [j2]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design. IET Circuits Devices Syst. 9(5): 362-369 (2015) - 2014
- [c7]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation. APCCAS 2014: 121-124 - [c6]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
An LSI implementation of a bit-parallel cellular multiplier over GF(24) using secure charge-sharing symmetric adiabatic logic. ISCAS 2014: 826-829 - [c5]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Process variation verification of low-power secure CSSAL AES S-box circuit. MWSCAS 2014: 21-24 - 2013
- [j1]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level. Microelectron. J. 44(6): 496-503 (2013) - [c4]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Low power secure CSSAL bit-parallel multiplier over GF(24) in 0.18μm CMOS technology. ECCTD 2013: 1-4 - [c3]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
DPA resistance of charge-sharing symmetric adiabatic logic. ISCAS 2013: 2581-2584 - [c2]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks. TSP 2013: 732-736 - 2011
- [c1]Câncio Monteiro, Yasuhiro Takahashi, Toshikazu Sekine:
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card. ISPACS 2011: 1-5
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