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Nobuyuki Hikichi
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2010 – 2019
- 2012
- [c8]Yukoh Matsumoto, Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Fumito Imura, Hiroshi Nakagawa, Masahiro Aoyagi:
Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications. COOL Chips 2012: 1-3
1990 – 1999
- 1996
- [c7]Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts. DAC 1996: 527-532 - 1995
- [c6]Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
A hardware/software codesign method for pipelined instruction set processor using adaptive database. ASP-DAC 1995 - [c5]Nguyen-Ngoc Bình, Masaharu Imai, Nobuyuki Hikichi:
A hardware/software partitioning algorithm for pipelined instruction set processor. EURO-DAC 1995: 176-181 - 1993
- [c4]Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Jun Sato, Nobuyuki Hikichi, Masaharu Imai:
PEAS-I: A hardware/software co-design system for ASIPs. EURO-DAC 1993: 2-7 - [c3]Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi:
An ASIP instruction set optimization algorithm with functional module sharing constraint. ICCAD 1993: 526-532 - 1992
- [c2]Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi:
An integer programming approach to instruction implementation method selection problem. EURO-DAC 1992: 106-111 - 1991
- [c1]Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi:
An Integrated Design Environment for Application Specific Integrated Processor. ICCD 1991: 414-417
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