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Jun Cao 0001
Person information
- affiliation: Broadcom Corporation, Irvine, CA
Other persons with the same name
- Jun Cao — disambiguation page
- Jun Cao 0002 — Arizona State University, Tempe, USA
- Jun Cao 0003 — University of Windsor, Ontario, Canada
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2020 – today
- 2024
- [j13]Bo Zhang
, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao, Karapet Khanoyan, Hamid Hatamkhani, Xiaochen Yang, Xin Meng, Alexander Wong, Jun Kim, Ping Jing
A 112-Gb/s Serial Link Transceiver With Three-Tap FFE and 18-Tap DFE Receiver for up to 43-dB Insertion Loss Channel in 7-nm FinFET Technology. IEEE J. Solid State Circuits 59(1): 8-18 (2024) - [c16]Guansheng Li, Adesh Garg, Tim He, Ullas Singh, Jiawen Zhang, Lakshmi P. Rao, Chang Liu, Meisam Honarvar Nazari, Yang Liu, Yong Liu, Heng Zhang, Tamer A. Ali, Hyo-Gyuem Rhew, Jiayoon Ru, Delong Cui, Ali Nazemi, Bo Zhang, Afshin Momtaz, Jun Cao:
18.1 A 600Gb/s DP-QAM64 Coherent Optical Transceiver Frontend with 4x105GS/s 8b ADC/DAC in 16nm CMOS. ISSCC 2024: 338-340 - 2023
- [c15]Bo Zhang, Anand Vasani, Ashutosh Sinha, Alireza Nilchi, Haitao Tong, Lakshmi P. Rao
A 112Gb/s Serial Link Transceiver With 3-tap FFE and 18-tap DFE Receiver for up to 43dB Insertion Loss Channel in 7nm FinFET Technology. ISSCC 2023: 108-109
2010 – 2019
- 2017
- [c14]Jun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz:
29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS. ISSCC 2017: 484-485 - 2016
- [c13]Delong Cui, Heng Zhang, Nick Huang, Ali Nazemi, Burak Çatli, Hyo-Gyuem Rhew, Bo Zhang, Afshin Momtaz, Jun Cao:
3.2 A 320mW 32Gb/s 8b ADC-based PAM-4 analog front-end with programmable gain control and analog peaking in 28nm CMOS. ISSCC 2016: 58-59 - [c12]Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j12]Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz:
A 40 nm CMOS 195 mW/55 mW Dual-Path Receiver AFE for Multi-Standard 8.5-11.5 Gb/s Serial Links. IEEE J. Solid State Circuits 50(2): 426-439 (2015) - [j11]Sui Huang, Jun Cao, Michael M. Green
An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS. IEEE J. Solid State Circuits 50(9): 2048-2060 (2015) - [c11]Guansheng Li, Wooram Lee, Delong Cui, Bo Zhang, Afshin Momtaz, Jun Cao:
Standing wave based clock distribution technique with application to a 10 × 11 Gbps transceiver in 28 nm CMOS. A-SSCC 2015: 1-4 - [c10]Ali Nazemi, Kangmin Hu, Burak Çatli, Delong Cui, Ullas Singh, Tim He, Zhi Chao Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS. ISSCC 2015: 1-3 - 2014
- [j10]Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A 780 mW 4 × 28 Gb/s Transceiver for 100 GbE Gearbox PHY in 40 nm CMOS. IEEE J. Solid State Circuits 49(12): 3116-3129 (2014) - [c9]Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao:
2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. ISSCC 2014: 40-41 - [c8]Sui Huang, Jun Cao, Michael M. Green:
8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS. ISSCC 2014: 152-153 - [c7]Adesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS. VLSIC 2014: 1-2 - 2013
- [j9]Jun Cao, Sui Huang, Michael M. Green:
Non-idealities in linear CDR phase detectors. Int. J. Circuit Theory Appl. 41(4): 331-346 (2013) - [j8]Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Deyi Pi, Anand Vasani, Zhi Chao Huang, Burak Çatli, Afshin Momtaz, Jun Cao:
A Sub-2 W 39.8-44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS. IEEE J. Solid State Circuits 48(12): 3219-3228 (2013) - [c6]Bharath Raghavan, Delong Cui, Ullas Singh, Hassan Maarefi, Dave Pi, Anand Vasani, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A sub-2W 39.8-to-44.6Gb/s transmitter and receiver chipset with SFI-5.2 interface in 40nm CMOS. ISSCC 2013: 32-33 - [c5]Bo Zhang, Ali Nazemi, Adesh Garg, Namik Kocaman, Mahmoud Reza Ahmadi, Mehdi Khanpour, Heng Zhang, Jun Cao, Afshin Momtaz:
A 195mW / 55mW dual-path receiver AFE for multistandard 8.5-to-11.5 Gb/s serial links in 40nm CMOS. ISSCC 2013: 34-35 - 2012
- [j7]Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Wei Zhang, Tamer A. Ali, Nick Huang, Bo Zhang, Afshin Momtaz, Jun Cao:
A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission. IEEE J. Solid State Circuits 47(12): 3249-3260 (2012) - [c4]Delong Cui, Bharath Raghavan, Ullas Singh, Anand Vasani, Zhi Chao Huang, Deyi Pi, Mehdi Khanpour, Ali Nazemi, Hassan Maarefi, Tamer A. Ali, Nick Huang, Wei Zhang, Bo Zhang, Afshin Momtaz, Jun Cao:
A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission. ISSCC 2012: 330-332 - 2011
- [j6]Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications. IEEE J. Solid State Circuits 46(12): 3089-3100 (2011) - [c3]Jun Cao, Sui Huang, Michael M. Green:
Non-idealities in linear CDR phase detectors. ECCTD 2011: 158-161 - [c2]Namik Kocaman, Adesh Garg, Bharath Raghavan, Delong Cui, Anand Vasani, Keith Tang, Deyi Pi, Haitao Tong, Siavash Fallahi, Wei Zhang, Ullas Singh, Jun Cao, Bo Zhang, Afshin Momtaz:
11.3Gb/s CMOS SONET-compliant transceiver for both RZ and NRZ applications. ISSCC 2011: 142-144 - 2010
- [j5]Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber. IEEE J. Solid State Circuits 45(6): 1172-1185 (2010)
2000 – 2009
- 2009
- [c1]Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz:
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber. ISSCC 2009: 370-371 - 2007
- [j4]Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori:
A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-µm CMOS. IEEE J. Solid State Circuits 42(4): 872-880 (2007) - 2002
- [j3]Jun Cao, Michael M. Green, Afshin Momtaz, Kambiz Vakilian, David Chung, Keh-Chee Jen, Mario Caresosa, Xin Wang, Wee-Guan Tan, Yijun Cai, Ichiro Fujimori, Armond Hairapetian:
OC-192 transmitter and receiver in standard 0.18-μm CMOS. IEEE J. Solid State Circuits 37(12): 1768-1780 (2002) - 2001
- [j2]Afshin Momtaz, Jun Cao, Mario Caresosa, Armond Hairapetian, David Chung, Kambiz Vakilian, Michael M. Green, Wee-Guan Tan, Keh-Chee Jen, Ichiro Fujimori, Yijun Cai:
A fully integrated SONET OC-48 transceiver in standard CMOS. IEEE J. Solid State Circuits 36(12): 1964-1973 (2001) - 2000
- [j1]Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama, Steve Kosic, Jun Cao, Shu-Lap Chan:
A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8× oversampling ratio. IEEE J. Solid State Circuits 35(12): 1820-1828 (2000)
Coauthor Index
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