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Ricardo Quislant
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2020 – today
- 2024
- [j13]Ivan Fernandez
, Christina Giannoula
MATSA: An MRAM-Based Energy-Efficient Accelerator for Time Series Analysis. IEEE Access 12: 36727-36742 (2024) - [j12]Ricardo Quislant
Exploring multiprocessor approaches to time series analysis. J. Parallel Distributed Comput. 188: 104855 (2024) - 2023
- [j11]Ricardo Quislant
Time series analysis acceleration with advanced vectorization extensions. J. Supercomput. 79(9): 10178-10207 (2023) - 2022
- [j10]Ivan Fernandez
TraTSA: A Transprecision Framework for Efficient Time Series Analysis. J. Comput. Sci. 63: 101784 (2022) - [j9]Manuel Pedrero
Speculative Barriers With Transactional Memory. IEEE Trans. Computers 71(1): 197-208 (2022) - [c14]Ivan Fernandez, Ricardo Quislant
Exploiting Near-Data Processing to Accelerate Time Series Analysis. ISVLSI 2022: 279-282 - [c13]Ricardo Quislant
Exploiting Vector Extennsions to Accelerate Time Series Analysis. PDP 2022: 55-62 - [i3]Ivan Fernandez, Ricardo Quislant
Exploiting Near-Data Processing to Accelerate Time Series Analysis. CoRR abs/2206.00938 (2022) - [i2]Ivan Fernandez, Aditya Manglik, Christina Giannoula, Ricardo Quislant
Accelerating Time Series Analysis via Processing using Non-Volatile Memories. CoRR abs/2211.04369 (2022) - 2020
- [c12]Ivan Fernandez, Ricardo Quislant
NATSA: A Near-Data Processing Accelerator for Time Series Analysis. ICCD 2020: 120-129 - [c11]Ivan Fernandez, Ricardo Quislant
Energy-Efficient Time Series Analysis Using Transprecision Computing. SBAC-PAD 2020: 83-90 - [i1]Ivan Fernandez, Ricardo Quislant, Christina Giannoula, Mohammed Alser, Juan Gómez-Luna, Eladio Gutiérrez, Oscar G. Plata, Onur Mutlu:
NATSA: A Near-Data Processing Accelerator for Time Series Analysis. CoRR abs/2010.02079 (2020)
2010 – 2019
- 2019
- [j8]Ricardo Quislant
Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions. J. Parallel Distributed Comput. 131: 103-119 (2019) - 2018
- [j7]Ricardo Quislant
Privatizing transactions for Lee's algorithm in commercial hardware transactional memory. J. Supercomput. 74(4): 1676-1694 (2018) - 2017
- [j6]Ricardo Quislant
Enhancing scalability in best-effort hardware transactional memory systems. J. Parallel Distributed Comput. 104: 73-87 (2017) - [j5]Ricardo Quislant
Leveraging irrevocability to deal with signature saturation in hardware transactional memory. J. Supercomput. 73(6): 2525-2557 (2017) - [j4]Ricardo Quislant
Lazy Irrevocability for Best-Effort Transactional Memory Systems. IEEE Trans. Parallel Distributed Syst. 28(7): 1919-1932 (2017) - 2016
- [c10]Ricardo Quislant
Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems. Euro-Par 2016: 251-263 - 2015
- [p1]Ricardo Quislant
Conflict Detection in Hardware Transactional Memory. Transactional Memory 2015: 127-149 - 2014
- [c9]Ricardo Quislant
Improving Signature Behavior by Irrevocability in Transactional Memory Systems. SBAC-PAD 2014: 120-127 - [c8]Ricardo Quislant
Scalability Analysis of Signatures in Transactional Memory Systems. SBAC-PAD 2014: 128-135 - 2013
- [j3]Ricardo Quislant
LS-Sig: Locality-Sensitive Signatures for Transactional Memory. IEEE Trans. Computers 62(2): 322-335 (2013) - [j2]Ricardo Quislant
Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets. IEEE Trans. Parallel Distributed Syst. 24(3): 506-519 (2013) - [c7]Miguel A. Gonzalez-Mesa, Ricardo Quislant
Exploring Irregular Reduction Support in Transactional Memory. ICA3PP (1) 2013: 257-266 - [c6]Miguel A. Gonzalez-Mesa, Ricardo Quislant
Dealing with Reduction Operations Using Transactional Memory. SBAC-PAD 2013: 128-135 - 2011
- [c5]Ricardo Quislant
Unified Locality-Sensitive Signatures for Transactional Memory. Euro-Par (1) 2011: 326-337 - [c4]Ricardo Quislant
Multiset signatures for transactional memory. ICS 2011: 43-52 - 2010
- [c3]Ricardo Quislant
Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification. IDEAL 2010: 162-169
2000 – 2009
- 2009
- [c2]Ricardo Quislant
Improving Signatures by Locality Exploitation for Transactional Memory. PACT 2009: 303-312 - 2008
- [j1]Ricardo Quislant
Teaching the Cache Memory System Using a Reconfigurable Approach. IEEE Trans. Educ. 51(3): 336-341 (2008) - 2007
- [c1]Ezequiel Herruzo
Simulating a Reconfigurable Cache System for Teaching Purposes. MSE 2007: 37-38
Coauthor Index
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last updated on 2024-08-05 20:19 CEST by the dblp team
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