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Ji-Hoon Lim
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2020 – today
- 2023
- [j8]Ji-Hoon Lim, Dong-In Lee, Ye-Ji Hyeon, Han-Shin Youn
:
Differential Power Processing Converter With Active Clamp Structure and Integrated Planar Transformer for Power Generation Optimization of Multiple Photovoltaic Submodules. IEEE Access 11: 5668-5678 (2023) - [c5]Ye-Ji Hyeon, Dong-In Lee, Seong-Wook Jeong, Ji-Hoon Lim, Han-Shin Youn:
Inductor Design of Interleaved Totem-Pole Bridgeless Boost PFC Based on Pareto Optimization. IECON 2023: 1-6 - [c4]Dong-In Lee, Ye-Ji Hyeon, Seong-Wook Jeong, Ji-Hoon Lim, Han-Shin Youn, Youn-Sik Lee, Dae-woo Lee:
An Improved PWM Method of Inverter PFC for Non-Isolated OBC. IECON 2023: 1-6
2010 – 2019
- 2016
- [j7]Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 51(8): 1890-1901 (2016) - [j6]Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 141-145 (2016) - 2013
- [j5]Ji-Hoon Lim, Won-Young Jung, Yong-Ju Kim, Inchae Song, Jae-Kyung Wee:
A Digitally-Controlled SMPS Using a Novel High-Resolution DPWM Generator Based on a Pseudo Relaxation-Oscillation Technique. IEICE Trans. Electron. 96-C(2): 277-284 (2013) - 2012
- [c3]Young-Kyun Park, Ji-Hoon Lim, Jae-Kyung Wee, Inchae Song:
One-chip multi-output SMPS using a shared digital controller and a pseudo relaxation oscillating technique. ISOCC 2012: 513-516 - 2011
- [j4]Young San Shin, Jae-Kyung Wee, Jong-Chan Ha, Ji-Hoon Lim, Yong-Ju Kim, Young-Sang Son:
A Seamless-Controlled Digital PLL Using Dual Loops for High Speed SoCs. J. Circuits Syst. Comput. 20(4): 741-756 (2011) - [j3]Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim
A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. IEEE J. Solid State Circuits 46(1): 107-118 (2011) - 2010
- [c2]Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim
A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. ISSCC 2010: 434-435
2000 – 2009
- 2008
- [j2]Seung-Jun Bae, Kwang-Il Park, Jeong-Don Ihm, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Yoon-Sik Park, Min-Sang Park, Hong-Kyong Lee, Sam-Young Bang, Gil-Shin Moon, Seokwon Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. IEEE J. Solid State Circuits 43(1): 121-131 (2008) - 2007
- [j1]Ji-Hoon Lim, Jong-Chan Ha, Won-Young Jung, Yong-Ju Kim, Jae-Kyung Wee:
A Novel High-Speed and Low-Voltage CMOS Level-Up/Down Shifter Design for Multiple-Power and Multiple-Clock Domain Chips. IEICE Trans. Electron. 90-C(3): 644-648 (2007) - [c1]Jeong-Don Ihm, Seung-Jun Bae, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Ho-Kyung Lee, Min-Sang Park, Sam-Young Bang, Mi-Jin Lee, Gil-Shin Moon, Young-Wook Jang, Suk-Won Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. ISSCC 2007: 492-617
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