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Chenyun Pan
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2020 – today
- 2024
- [j6]Zhenlin Pei
, Hsiao-Hsuan Liu
Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. IEEE Trans. Circuits Syst. I Regul. Pap. 71(10): 4597-4610 (2024) - [c19]Sheng Lu, Liuting Shang, Sungyong Jung, Chenyun Pan:
Emerging Reconfigurable Logic Device Based FPGA Design and Optimization. ISQED 2024: 1-8 - [c18]Sheng Lu, Liuting Shang, Sungyong Jung, Yichen Zhang, Chenyun Pan:
A Novel Delay-Aware Packing Algorithm for FPGA Architecture Using RFET. MWSCAS 2024: 362-366 - [i4]Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos:
QPUF 2.0: Exploring Quantum Physical Unclonable Functions for Security-by-Design of Energy Cyber-Physical Systems. CoRR abs/2410.12702 (2024) - 2023
- [j5]Chengchen Mao, Qilian Liang
A statistical approach for neural network pruning with application to internet of things. EURASIP J. Wirel. Commun. Netw. 2023(1): 44 (2023) - [j4]Chengchen Mao, Zongwen Mu, Qilian Liang
Deep learning in physical layer communications: Evolution and prospects in 5G and 6G networks. IET Commun. 17(16): 1863-1876 (2023) - [j3]Liuting Shang
Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis. IEEE Open J. Comput. Soc. 4: 50-61 (2023) - [c17]Zhenlin Pei
Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. ACM Great Lakes Symposium on VLSI 2023: 159-162 - [c16]Venkata K. V. V. Bathalapalli, Saraju P. Mohanty, Chenyun Pan, Elias Kougianos:
QPUF: Quantum Physical Unclonable Functions for Security-by-Design of Industrial Internet-of-Things. iSES 2023: 296-301 - [c15]Zhenlin Pei
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. ISQED 2023: 1 - [c14]Liuting Shang, Sheng Lu, Sungyong Jung, Chenyun Pan:
Novel Fence Generation Methods for Accelerating Reconfigurable Exact Synthesis. MWSCAS 2023: 506-510 - [c13]Sheng Lu, Zhenlin Pei
A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices. MWSCAS 2023: 1123-1127 - 2020
- [c12]Liuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan:
Fast Linear Programming Optimization Using Crossbar-Based Analog Accelerator. ISVLSI 2020: 276-281
2010 – 2019
- 2019
- [j2]Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi
A Mixed Signal Architecture for Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 15(2): 19:1-19:26 (2019) - 2018
- [c11]Victor Huang, Chenyun Pan, Azad Naeemi
Generic system-level modeling and optimization for beyond CMOS device applications. ISQED 2018: 196-200 - [i3]Qiuwen Lou, Chenyun Pan, John McGuinness, András Horváth, Azad Naeemi, Michael T. Niemier, Xiaobo Sharon Hu:
A mixed signal architecture for convolutional neural networks. CoRR abs/1811.02636 (2018) - 2017
- [c10]Chenyun Pan, Azad Naeemi
Beyond-CMOS non-Boolean logic benchmarking: Insights and future directions. DATE 2017: 133-138 - [i2]Chenyun Pan, Azad Naeemi:
Beyond-CMOS Device Benchmarking for Boolean and Non-Boolean Logic Applications. CoRR abs/1711.04295 (2017) - 2016
- [c9]Victor Huang, Chenyun Pan, Dmitry Yakimets, Praveen Raghavan, Azad Naeemi
Device/system performance modeling of stacked lateral NWFET logic. ISQED 2016: 215-220 - [c8]Javaneh Mohseni, Chenyun Pan, Azad Naeemi
Performance modeling and optimization for on-chip interconnects in 3D memory arrays. ISQED 2016: 252-257 - [c7]Divya Prasad, Chenyun Pan, Azad Naeemi
Impact of interconnect variability on circuit performance in advanced technology nodes. ISQED 2016: 398-404 - [i1]Chenyun Pan, Azad Naeemi:
A Proposal for Energy-Efficient Cellular Neural Network based on Spintronic Devices. CoRR abs/1604.04584 (2016) - 2015
- [j1]Chenyun Pan, Azad Naeemi
A Fast System-Level Design Methodology for Heterogeneous Multi-Core Processors Using Emerging Technologies. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 75-87 (2015) - [c6]Chenyun Pan, Praveen Raghavan, Francky Catthoor, Zsolt Tokei
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. ISQED 2015: 599-603 - 2014
- [c5]Azad Naeemi
BEOL Scaling Limits and Next Generation Technology Prospects. DAC 2014: 26:1-26:6 - [c4]Chenyun Pan, Saibal Mukhopadhyay, Azad Naeemi
An analytical approach to system-level variation analysis and optimization for multi-core processor. ISQED 2014: 99-106 - 2013
- [c3]Chenyun Pan, Ahmet Ceyhan, Azad Naeemi
System-level optimization and benchmarking for InAs nanowire based gate-all-around tunneling FETs. ISQED 2013: 196-202 - 2012
- [c2]Chenyun Pan, Azad Naeemi
System-level optimization and benchmarking of graphene PN junction logic system based on empirical CPI model. ICICDT 2012: 1-5 - [c1]Chenyun Pan, Azad Naeemi
Device- and system-level performance modeling for graphene P-N junction logic. ISQED 2012: 262-269
Coauthor Index
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