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Arghavan Asad
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2020 – today
- 2024
- [j9]Rupinder Kaur, Arghavan Asad, Farah A. Mohammadi:
A Comprehensive Review of Processing-in-Memory Architectures for Deep Neural Networks. Comput. 13(7): 174 (2024) - 2023
- [j8]Arghavan Asad, Farah A. Mohammadi:
Godiva: green on-chip interconnection for DNNs. J. Supercomput. 79(3): 2404-2430 (2023) - 2022
- [j7]Arghavan Asad, Rupinder Kaur
, Farah Mohammadi:
A Survey on Memory Subsystems for Deep Neural Network Accelerators. Future Internet 14(5): 146 (2022) - [c22]Arghavan Asad, Rupinder Kaur, Farah A. Mohammadi:
Noise Suppression Using Gated Recurrent Units and Nearest Neighbor Filtering. CSCI 2022: 368-372 - [c21]Arghavan Asad, Farah A. Mohammadi:
NeuroTower: A 3D Neuromorphic Architecture with Low-Power TSVs. FTC (3) 2022: 227-236 - [i2]Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy:
Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression. CoRR abs/2201.00774 (2022) - 2021
- [j6]Furat Al-Obaidy
A Power-Aware Hybrid Cache for Chip-Multi Processors Based on Neural Network Prediction Technique. Int. J. Parallel Program. 49(3): 326-346 (2021) - 2020
- [c20]Arghavan Asad, Furat Al-Obaidy, Farah Mohammadi:
Efficient Power Consumption using Hybrid Emerging Memory Technology for 3D CMPs. LASCAS 2020: 1-4
2010 – 2019
- 2019
- [j5]Arghavan Asad
An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors. J. Circuits Syst. Comput. 28(13): 1950224:1-1950224:30 (2019) - [c19]Furat Al-Obaidy, Arghavan Asad, Farah Mohammadi:
Power-Management based on Reconfigurable Last-Cache level on Non-volatile Memories in Chip-Multi processors. CCECE 2019: 1-4 - [c18]Furat Al-Obaidy, Arghavan Asad, Farah Mohammadi:
Reconfigurable Hybrid Cache Hierarchy in 3D Chip-Multi Processors Based on a Convex optimization Method. CCECE 2019: 1-6 - [i1]Salman Onsori, Arghavan Asad, Kaamran Raahemifar, Mahmood Fathy:
An Energy-Efficient Heterogeneous Memory Architecture for Future Dark Silicon Embedded Chip-Multiprocessors. CoRR abs/1912.06576 (2019) - 2018
- [j4]Arghavan Asad, Aniseh Dorostkar, Farah Mohammadi:
A novel power model for future heterogeneous 3D chip-multiprocessors in the dark silicon age. EURASIP J. Embed. Syst. 2018(1): 3 (2018) - [c17]Pooneh Safayenikoo, Arghavan Asad, Farah Mohammadi:
An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses. CCECE 2018: 1-4 - [c16]Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines. ISCAS 2018: 1-5 - [c15]Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy
Optimization-based reconfigurable approach for low-power 3D chip-multiprocessors. LASCAS 2018: 1-4 - 2017
- [j3]Arghavan Asad, Mahmood Fathy
Power Modeling and Runtime Performance Optimization of Power Limited Many-Core Systems Based on a Dynamic Adaptive Approach. J. Low Power Electron. 13(2): 166-195 (2017) - [j2]Arghavan Asad, Ozcan Ozturk, Mahmood Fathy
Optimization-based power and thermal management for dark silicon aware 3D chip multiprocessors using heterogeneous cache hierarchy. Microprocess. Microsystems 51: 76-98 (2017) - [c14]Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs. CCECE 2017: 1-5 - [c13]Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors. CCECE 2017: 1-4 - [c12]Aniseh Dorostkar, Arghavan Asad, Mahmood Fathy
Optimal Placement of Heterogeneous Uncore Component in 3D Chip-Multiprocessors. DSD 2017: 547-551 - [c11]Pooneh Safayenikoo, Arghavan Asad, Mahmood Fathy
An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors. ISQED 2017: 373-378 - [c10]Fatemeh Arezoomand, Arghavan Asad, Mahdi Fazeli
Reliability and Power Optimization in 3D-Stacked Cache Using a Run-Time Reconfiguration Procedure. MCSoC 2017: 75-82 - [c9]Fatemeh Arezoomand, Arghavan Asad, Mahdi Fazeli
Energy aware and reliable STT-RAM based cache design for 3D embedded chip-multiprocessors. ReCoSoC 2017: 1-8 - 2016
- [c8]Salman Onsori, Arghavan Asad, Kaamran Raahemifar, Mahmood Fathy
High performance 3D CMP design with stacked hybrid memory architecture in the dark silicon era using a convex optimization model. ISCAS 2016: 2607-2610 - [c7]Pooneh Safayenikoo, Arghavan Asad, Kaamran Raahemifar, Mahmood Fathy
UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk. NoCArc@MICRO 2016: 39-44 - 2015
- [c6]Arghavan Asad, Ozcan Ozturk, Mahmood Fathy
Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processors. DSD 2015: 314-321 - [c5]Salman Onsori, Arghavan Asad, Özcan Özturk, Mahmood Fathy
Hybrid stacked memory architecture for energy efficient embedded chip-multiprocessors based on compiler directed approach. IGSC 2015: 1-7 - [c4]Ashkan Sadeghi, Kaamran Raahemifar, Mahmood Fathy
Lighting the Dark-Silicon 3D Chip Multi-processors by Exploiting Heterogeneity in Cache Hierarchy. MCSoC 2015: 182-186 - [c3]Sobhan Niknam
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. ReCoSoC 2015: 1-8 - 2011
- [j1]Asghar Keshtkar, Amir Maghoul, Ali Kalantarnia, Arghavan Asad:
Design considerations to affect on shielding effectiveness for conductive enclosure. IEICE Electron. Express 8(13): 1047-1055 (2011)
2000 – 2009
- 2009
- [c2]Amir Ehsani Zonouz, Mehrdad Seyrafi, Arghavan Asad, Mohsen Soryani
A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. DSD 2009: 473-480 - [c1]Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. ReConFig 2009: 290-295
Coauthor Index
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last updated on 2024-08-10 00:30 CEST by the dblp team
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