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Tadao Nakamura
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2020 – today
- 2023
- [j32]Koji Nagata
, Do Ngoc Diep, Tadao Nakamura:
Two symmetric measurements may cause an unforeseen effect. Quantum Inf. Process. 22(2): 94 (2023) - 2022
- [j31]Koji Nagata
Computational complexity in high-dimensional quantum computing. Quantum Mach. Intell. 4(2): 1-8 (2022) - 2021
- [i2]Koji Nagata, Renata Wong, Do Ngoc Diep, Tadao Nakamura:
Quantum cryptography based on an algorithm for determining simultaneously all the mappings of a Boolean function. IACR Cryptol. ePrint Arch. 2021: 758 (2021) - 2020
- [i1]Do Ngoc Diep, Koji Nagata, Tadao Nakamura:
Nonparametric Regression Quantum Neural Networks. CoRR abs/2002.02818 (2020)
2010 – 2019
- 2019
- [c41]Tadao Nakamura:
An Introduction to Marching Memory (MM). 3DIC 2019: 1-3 - 2017
- [j30]Ryota Yasudo
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66(4): 702-716 (2017) - [c40]Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash:
Panel discussions: "Cool chips for the next decade". COOL Chips 2017: 1-3 - 2016
- [c39]Tadao Nakamura:
Message from the advisory committee chair. COOL Chips 2016: iii - 2015
- [c38]Ryota Yasudo
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS 2015: 16:1-16:8 - 2014
- [j29]Yukinori Sato
Identifying Program Loop Nesting Structures during Execution of Machine Code. IEICE Trans. Inf. Syst. 97-D(9): 2371-2385 (2014) - [c37]Ryota Yasudo
A low power NoC router using the marching memory through type. COOL Chips 2014: 1-3 - [c36]Tadao Nakamura:
Message from the advisory committee chair. COOL Chips 2014: iii - [c35]Ryota Yasudo
Design of a low power NoC router using Marching Memory Through type. NOCS 2014: 111-118 - 2013
- [j28]Koji Nagata, Tadao Nakamura:
An additional condition for Bell experiments for accepting local realistic theories. Quantum Inf. Process. 12(12): 3785-3789 (2013) - [c34]Tadao Nakamura, Yoriko Mizushima, Hideki Kitada, Young-Suk Kim, Nobuhide Maeda, Shoichi Kodama, Ryuichi Sugie
Influence of wafer thinning process on backside damage in 3D integration. 3DIC 2013: 1-6 - [c33]Tadao Nakamura:
Message from the Advisory Committee Chair. COOL Chips 2013: iii - 2012
- [c32]Yukinori Sato
Whole program data dependence profiling to unveil parallel regions in the dynamic execution. IISWC 2012: 69-80 - [c31]Yukinori Sato
Evaluating reconfigurable dataflow computing using the Himeno benchmark. ReConFig 2012: 1-7 - 2011
- [c30]Nobuhide Maeda, Young-Suk Kim, Y. Hikosaka, T. Eshita, Hideki Kitada, K. Fujimoto, Yoriko Mizushima, K. Suzuki, Tadao Nakamura, Akihito Kawai, Kazuhisa Arai, Takayuki Ohba:
Development of ultra-thinning technology for logic and memory heterogeneous stack applications. 3DIC 2011: 1-4 - [c29]Yukinori Sato
On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. Conf. Computing Frontiers 2011: 25 - 2010
- [c28]K. Suzuki, Tadao Nakamura:
Development of a peristaltic pump based on bowel peristalsis using for artificial rubber muscle. IROS 2010: 3085-3090
2000 – 2009
- 2009
- [j27]Hideharu Amano, Tadao Nakamura:
Guest Editors' Introduction: ICFPT 2007. ACM Trans. Reconfigurable Technol. Syst. 2(2): 7:1-7:2 (2009) - 2007
- [j26]Yukinori Sato
Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation. IEICE Trans. Inf. Syst. 90-D(3): 627-636 (2007) - 2006
- [c27]Yoshiyuki Kaeriyama, Daichi Zaitsu, Kazuhiko Komatsu
Ray Tracing Hardware System Using Plane-Sphere Intersections. FPL 2006: 1-6 - 2005
- [j25]Takeshi Miura, Kentaro Sano, Ken-ichi Suzuki, Tadao Nakamura:
A Competitive Learning Algorithm with Controlling Maximum Distortion. J. Adv. Comput. Intell. Intell. Informatics 9(2): 166-174 (2005) - [c26]Yukinori Sato, Ken-ichi Suzuki, Tadao Nakamura:
An Operand Status Based Instruction Steering Scheme for Clustered Architectures. CDES 2005: 168-174 - [c25]Yukinori Sato
Cooperation of Neighboring PEs in Clustered Architectures. SBAC-PAD 2005: 134-142 - 2004
- [j24]Kentaro Sano, Yusuke Kobayashi, Tadao Nakamura:
Differential coding scheme for efficient parallel image composition on a PC cluster system. Parallel Comput. 30(2): 285-299 (2004) - [j23]Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa
Efficient parallel processing of competitive learning algorithms. Parallel Comput. 30(12): 1361-1383 (2004) - [c24]Shintaro Momose, Kentaro Sano, K. Suzuki, Tadao Nakamura:
Parallel competitive learning algorithm for fast codebook design on partitioned space. CLUSTER 2004: 449-457 - [c23]Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-ichi Suzuki, Tadao Nakamura:
A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. ITCC (1) 2004: 572-578 - 2003
- [c22]Tadao Nakamura:
Toward Architecting and Designing Novel Computers. Asia-Pacific Computer Systems Architecture Conference 2003: 8-13 - 2002
- [c21]Tomoyuki Nagase, Takashi Araki, Yoshio Yoshioka, Tadao Nakamura:
Moderating traffic flow over conventional ATM service. ISCC 2002: 659-663 - [c20]Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Taira Nakajima, C. D. Lima, Hiroaki Kobayashi, Tadao Nakamura:
Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks. IASTED PDCS 2002: 578-582 - [c19]C. D. Lima, Kentaro Sano, Tadao Nakamura:
Hardware Support for Concurrent Execution of Loops Containing Loop-carried Data Dependences. IASTED PDCS 2002: 718-723 - [c18]Clecio Donizete Lima, Tadao Nakamura:
Exploiting Loop-Level Parallelism with the Shift Architecture. SBAC-PAD 2002: 184-194 - 2001
- [c17]Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura:
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. ICCD 2001: 462-467 - [c16]Emad Rashid, Takashi Araki, Tadao Nakamura:
An Active Network for Improving Performance of Traffic Flow over Conventional ATM Service. ICN (2) 2001: 620-627 - [c15]Emad Rashid, Yoshio Yoshioka, Takashi Araki, Tadao Nakamura:
Variable-Length Coding based on Bent Sequences for W.ireless Advertising. ISCC 2001: 568-572 - [c14]Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura:
Scaling Up Of Wave Pipelines. VLSI Design 2001: 439-445 - 2000
- [j22]Lei Li
Fast parallel algorithms for vandermonde determinants. Int. J. Comput. Math. 73(4): 479-486 (2000) - [j21]Tadao Nakamura:
Cool Chips III. IEEE Micro 20(6): 83-84 (2000) - [c13]Hiroshi Sasaki, Hitoshi Maruyama, Hideaki Tsukioka, Nobuyoshi Shoji, Hiroaki Kobayashi, Tadao Nakamura:
Reconfigurable synchronized dataflow processor. ASP-DAC 2000: 27-28
1990 – 1999
- 1999
- [j20]Tadao Nakamura:
Introducing cool chips. IEEE Micro 19(4): 9-10 (1999) - [j19]Ken-ichi Suzuki, Nobuyuki Oba, Shigenori Shimizu, Hiroaki Kobayashi, Tadao Nakamura:
Time stamp invalidation of TLB-unified cache and its performance evaluation. Syst. Comput. Jpn. 30(11): 94-106 (1999) - [j18]Takuya Nakaike, Takehito Sasaki, Masayuki Katahira, Hiroaki Kobayashi, Tadao Nakamura:
A scheduling method for instruction-level parallel processing of vectorand scalar instructions. Syst. Comput. Jpn. 30(13): 23-33 (1999) - [c12]Taira Nakajima, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura:
A self-organizing network system forming memory from nonstationary probability distributions. IJCNN 1999: 742-745 - 1998
- [c11]Kouji Takano, Takehito Sasaki, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura:
Automated Design of Wave Pipelined Multiport Register Files. ASP-DAC 1998: 197-202 - 1997
- [j17]Jie Hu, Tadao Nakamura, Lei Li:
Convergence, Complexity and Simulation of Monotone Asynchronous Iterative Method for Computing Fixed Point on a Distributed Computer. Parallel Algorithms Appl. 11(1-2): 1-11 (1997) - [j16]Jie Hu, Tadao Nakamura, Lei Li:
Asynchronous Monotone Newton Iterative Method on Distributed Computers. Parallel Algorithms Appl. 12(4): 341-348 (1997) - [j15]Masafumi Takahashi, Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura:
Decoupled modified-bit cache. Syst. Comput. Jpn. 28(6): 49-59 (1997) - [c10]Kentaro Sano, Hiroyuki Kitajima, Hiroaki Kobayashi, Tadao Nakamura:
Parallel processing of the shear-warp factorization with the binary-swap method on a distributed-memory multiprocessor system. PRS 1997: 87-94 - 1996
- [j14]Masaaki Nishi, Junji Furuya, Tadao Nakamura:
A construction of back-propagation neural networks including time delay elements (BPD). Syst. Comput. Jpn. 27(10): 79-88 (1996) - [j13]Lei Li
A Simple Parallel Algorithm for Polynomial Evaluation. SIAM J. Sci. Comput. 17(1): 260-262 (1996) - [c9]Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh, Tadao Nakamura:
A Hierarchical Parallel Processing System for the Multipass-Rendering Method. IPPS 1996: 62-67 - 1995
- [j12]Jie Hu, Lei Li
A Divide-and-inner Product Parallel Algorithm for Polynomial Evaluation. Parallel Algorithms Appl. 6(1): 63-66 (1995) - [j11]Lei Li
The Convergence of Asynchronous Iterations for the Fixed Point of a Splitting Operator. Parallel Algorithms Appl. 7(3-4): 229-235 (1995) - [c8]Jie Hu, Tadao Nakamura, Lei Li:
The Convergence of Asynchronous Monotone Newton Iterations on Distributed Computer. PP 1995: 106-107 - 1994
- [c7]Masayuki Katahira, Takehito Sasaki, Hong Shen, Hiroaki Kobayashi, Tadao Nakamura:
Software pipelining for Jetpipeline architecture. ISPAN 1994: 127-134 - 1993
- [c6]Masa-Aki Fukase, Tadao Nakamura:
Parallel Processing and Hardware Support of Symbols. ICTAI 1993: 450-451 - [c5]Nobuyuki Oba, Hiroaki Kobayashi, Tadao Nakamura:
An Adaptive Network Routing Method by Electrical-Circuit Modeling. INFOCOM 1993: 586-592 - 1991
- [c4]Masa-Aki Fukase, Tadao Nakamura:
Semiparallel execution of compiled Lisp programs. COMPSAC 1991: 719-724
1980 – 1989
- 1988
- [j10]Hiroaki Kobayashi, Satoshi Nishimura, Hideyuki Kubota, Tadao Nakamura, Yoshiharu Shigei:
Load balancing strategies for a parallel ray-tracing system based on constant subdivision. Vis. Comput. 4(4): 197-209 (1988) - 1987
- [j9]Nobuyuki Oba, Tadao Nakamura, Yoshiharu Shigei:
An adaptive routing method for computer networks by electric-circuit modeling. Syst. Comput. Jpn. 18(3): 65-78 (1987) - [j8]Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Takahiko Murayama, Yoshio Yoshioka:
Realization of computers using programmable logic units. Syst. Comput. Jpn. 18(8): 47-56 (1987) - [j7]Takahiko Murayama, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Yoshio Yoshioka:
Performance evaluation of a computer using programmable logic units. Syst. Comput. Jpn. 18(8): 57-66 (1987) - [j6]Takahiko Murayama, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei, Yoshio Yoshioka:
Characteristics of a programmable logic unit. Syst. Comput. Jpn. 18(9): 31-43 (1987) - [j5]Hiroaki Kobayashi, Tadao Nakamura, Yoshiharu Shigei:
Parallel processing of an object space for image synthesis using ray tracing. Vis. Comput. 3(1): 13-22 (1987) - 1986
- [j4]Jun Miyajima, Noboru Endo, Tadao Nakamura, Yoshiharu Shigei:
Matrix representation of programs within an intelligent link. Syst. Comput. Jpn. 17(1): 11-18 (1986) - [j3]Nobuyuki Oba, Tadao Nakamura, Yoshiharu Shigei:
Signal processing on a parallel pipeline-structured data-flow computer system. Syst. Comput. Jpn. 17(4): 9-16 (1986) - [j2]Noboru Endo, Tadao Nakamura, Yoshiharu Shigei:
A Hierarchical General-Purpose Pipeline System. Syst. Comput. Jpn. 17(4): 69-76 (1986) - 1985
- [j1]Masayuki Tomisawa, Hidekazu Yamada, Tadao Nakamura, Yoshiharu Shigei:
Evaluating the parallelism of the feed-forward machine and algorithms of the machine. Syst. Comput. Jpn. 16(4): 37-45 (1985) - 1984
- [c3]Tadao Nakamura, Hiroaki Kobayashi, Jun Miyajima, Noboru Endo, Yoshiharu Shigei:
A Language Processor of an Intelligent Link System. ICC (2) 1984: 527-530 - [c2]Kuninobu Tanno, Tadao Nakamura, Risaburo Sato:
An Analysis of the Receiving Behaviour of a Window Flow Control Mechanism in Packet Switching Networks. ICC (3) 1984: 1331-1334 - 1981
- [c1]Makoto Hasegawa, Tadao Nakamura, Yoshiharu Shigei:
Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging. ISCA 1981: 367-372
Coauthor Index
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