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Alberto Allara
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2000 – 2009
- 2000
- [j1]Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice:
A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller. IEEE Des. Test Comput. 17(2): 60-72 (2000)
1990 – 1999
- 1998
- [c5]Alberto Allara, Massimo Bombana, Patrizia Cavalloro, Wolfgang Nebel, Wolfram Putzke-Röming, Martin Radetzki:
ATM Cell Modelling using Objective VHDL. ASP-DAC 1998: 261-264 - [c4]Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto:
A Model for System-Level Timed Analysis and Profiling. DATE 1998: 204-210 - [c3]Alberto Allara, Carlo Brandolese, William Fornaciari, Fabio Salice, Donatella Sciuto:
System-level performance estimation strategy for sw and hw. ICCD 1998: 48-53 - 1997
- [c2]Alberto Allara, S. Filipponi, Fabio Salice, William Fornaciari, Donatella Sciuto:
A Flexible Model for Evaluating the Behavior of Hardware/Software Systems. CODES 1997: 109-114 - [c1]Alberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto:
Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. ICCD 1997: 400-405
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