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Zhiqiang Cui
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2020 – today
- 2024
- [j7]Zhiqiang Cui
, Hongli Jia, Qi Gao, Haowen Song:
Maintenance Spare Parts Prediction Based on Multilevel Migration Learning CNN-ISE-Attention-BiLSTM. IEEE Access 12: 15208-15221 (2024) - 2023
- [j6]Zhiqiang Cui, Zhaoxia Pu
The Use of Regional Data Assimilation to Improve Numerical Simulations of Diurnal Characteristics of Precipitation during an Active Madden-Julian Oscillation Event over the Maritime Continent. Remote. Sens. 15(9): 2405 (2023)
2010 – 2019
- 2014
- [c8]Zhiqiang Cui, Zhongfeng Wang, Xinming Huang:
Multilevel error correction scheme for MLC flash memory. ISCAS 2014: 201-204 - 2012
- [i1]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-Complexity Column-Layered Decoding and Implementation for LDPC Codes. CoRR abs/1204.2577 (2012) - 2011
- [j5]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang:
Reduced-complexity column-layered decoding and implementation for LDPC codes. IET Commun. 5(15): 2177-2186 (2011)
2000 – 2009
- 2009
- [j4]Zhiqiang Cui, Zhongfeng Wang, Youjian Liu
High-Throughput Layered LDPC Decoding Architecture. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 582-587 (2009) - [c7]Jinjin He, Zhongfeng Wang, Zhiqiang Cui, Li Li:
Towards an Optimal Trade-off of Viterbi Decoder Design. ISCAS 2009: 3030-3033 - 2008
- [j3]Zhiqiang Cui, Zhongfeng Wang:
Improved low-complexity low-density parity-check decoding. IET Commun. 2(8): 1061-1068 (2008) - [c6]Zhiqiang Cui, Zhongfeng Wang, Xinmiao Zhang, Qingwei Jia:
Efficient decoder design for high-throughput LDPC decoding. APCCAS 2008: 1640-1643 - [c5]Zhiqiang Cui, Zhongfeng Wang:
Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI 2008: 457-462 - 2007
- [j2]Zhongfeng Wang, Zhiqiang Cui:
Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15(1): 104-114 (2007) - [j1]Zhongfeng Wang, Zhiqiang Cui:
A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 483-488 (2007) - [c4]Zhiqiang Cui, Zhongfeng Wang:
Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS 2007: 917-920 - [c3]Zhiqiang Cui, Zhongfeng Wang:
Studies on Practical Low Complexity Decoding of Low-Density Parity-Check Codes. SiPS 2007: 216-221 - 2006
- [c2]Zhiqiang Cui, Zhongfeng Wang:
A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006 - [c1]Zhiqiang Cui, Zhongfeng Wang:
Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS 2006
Coauthor Index
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