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Naveen Muralimanohar
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2010 – 2019
- 2018
- [j10]Anirban Nag, Rajeev Balasubramonian, Vivek Srikumar, Ross Walker, Ali Shafiee, John Paul Strachan, Naveen Muralimanohar:
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. IEEE Micro 38(5): 41-49 (2018) - [i1]Anirban Nag, Ali Shafiee, Rajeev Balasubramonian, Vivek Srikumar, Naveen Muralimanohar:
Newton: Gravitating Towards the Physical Limits of Crossbar Acceleration. CoRR abs/1803.06913 (2018) - 2017
- [j9]Rajeev Balasubramonian, Andrew B. Kahng, Naveen Muralimanohar, Ali Shafiee, Vaishnav Srinivas
:
CACTI 7: New Tools for Interconnect Exploration in Innovative Off-Chip Memories. ACM Trans. Archit. Code Optim. 14(2): 14:1-14:25 (2017) - 2016
- [j8]Babak Falsafi, Mircea Stan
Near-Memory Data Services. IEEE Micro 36(1): 6-13 (2016) - [c29]Arjun Deb, Paolo Faraboschi
Enabling technologies for memory compression: Metadata, mapping, and prediction. ICCD 2016: 17-24 - [c28]Ali Shafiee, Anirban Nag, Naveen Muralimanohar, Rajeev Balasubramonian, John Paul Strachan, Miao Hu, R. Stanley Williams
ISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars. ISCA 2016: 14-26 - 2015
- [j7]Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models. IEEE Trans. Very Large Scale Integr. Syst. 23(7): 1254-1267 (2015) - [c27]Cong Xu, Dimin Niu, Naveen Muralimanohar, Rajeev Balasubramonian, Tao Zhang, Shimeng Yu
Overcoming the challenges of crossbar resistive memory architectures. HPCA 2015: 476-488 - [c26]Manjunath Shevgoor, Naveen Muralimanohar, Rajeev Balasubramonian, Yoocharn Jeon:
Improving memristor memory with sneak current sharing. ICCD 2015: 549-556 - [c25]Ke Chen, Sheng Li, Jung Ho Ahn
History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. ICS 2015: 251-261 - 2014
- [j6]HanBin Yoon, Justin Meza, Naveen Muralimanohar, Norman P. Jouppi, Onur Mutlu:
Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories. ACM Trans. Archit. Code Optim. 11(4): 40:1-40:25 (2014) - 2013
- [c24]Cong Xu, Dimin Niu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Understanding the trade-offs in multi-level cell ReRAM memory design. DAC 2013: 108:1-108:6 - [c23]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost. ICCAD 2013: 17-23 - 2012
- [j5]Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
Free-p: A Practical End-to-End Nonvolatile Memory Protection Mechanism. IEEE Micro 32(3): 79-87 (2012) - [j4]Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
Optical High Radix Switch Design. IEEE Micro 32(3): 100-109 (2012) - [c22]Ke Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi:
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. DATE 2012: 33-38 - [c21]Niladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads. HPCA 2012: 41-52 - [c20]Norman P. Jouppi, Andrew B. Kahng, Naveen Muralimanohar, Vaishnav Srinivas
CACTI-IO: CACTI with off-chip power-area-timing models. ICCAD 2012: 294-301 - [c19]Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar, Parthasarathy Ranganathan:
BOOM: Enabling mobile memory based low-power server DIMMs. ISCA 2012: 25-36 - [c18]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
LOT-ECC: Localized and tiered reliability mechanisms for commodity memory systems. ISCA 2012: 285-296 - [c17]Dimin Niu, Cong Xu, Naveen Muralimanohar, Norman P. Jouppi, Yuan Xie:
Design trade-offs for high density cross-point resistive memory. ISLPED 2012: 209-214 - 2011
- [b2]Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar:
Multi-Core Cache Hierarchies. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011, ISBN 978-3-031-00606-7 - [j3]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Hybrid checkpointing using emerging nonvolatile memories for future exascale systems. ACM Trans. Archit. Code Optim. 8(2): 6:1-6:29 (2011) - [c16]Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
FREE-p: Protecting non-volatile memory against both hard and soft errors. HPCA 2011: 466-477 - [c15]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems. ISCA 2011: 425-436 - [c14]Nathan L. Binkert, Al Davis, Norman P. Jouppi, Moray McLaren, Naveen Muralimanohar, Robert Schreiber, Jung Ho Ahn
The role of optics in future high radix switch design. ISCA 2011: 437-448 - [c13]Sheng Li, Ke Chen, Ming-yu Hsieh, Naveen Muralimanohar, Chad D. Kersey, Jay B. Brockman, Arun F. Rodrigues, Norman P. Jouppi:
System implications of memory reliability in exascale computing. SC 2011: 46:1-46:12 - [p1]Jung Ho Ahn
CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study. Low Power Networks-on-Chip 2011: 223-254 - 2010
- [c12]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian:
Towards scalable, energy-efficient, bus-based on-chip networks. HPCA 2010: 1-12 - [c11]Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Rethinking DRAM design and organization for energy-constrained multi-cores. ISCA 2010: 175-186 - [c10]Xiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi:
Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support. SC 2010: 1-11
2000 – 2009
- 2009
- [b1]Naveen Muralimanohar:
Wire Aware Cache Architecture. University of Utah, USA, 2009 - [c9]Aniruddha N. Udipi, Naveen Muralimanohar, Rajeev Balasubramonian:
Non-uniform power access in large caches with low-swing wires. HiPC 2009: 59-68 - [c8]Niti Madan, Li Zhao, Naveen Muralimanohar, Aniruddha N. Udipi, Rajeev Balasubramonian, Ravishankar R. Iyer, Srihari Makineni, Donald Newell:
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. HPCA 2009: 262-274 - [c7]Xiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie:
Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. SC 2009 - 2008
- [j2]Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Architecting Efficient Interconnects for Large Caches with CACTI 6.0. IEEE Micro 28(1): 69-79 (2008) - [c6]Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian:
Scalable and reliable communication for hardware transactional memory. PACT 2008: 144-154 - 2007
- [c5]Naveen Muralimanohar, Rajeev Balasubramonian:
Interconnect design considerations for large NUCA caches. ISCA 2007: 369-380 - [c4]Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. MICRO 2007: 3-14 - 2006
- [j1]Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter:
Leveraging Wire Properties at the Microarchitecture Level. IEEE Micro 26(6): 40-52 (2006) - [c3]Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter:
Interconnect-Aware Coherence Protocols for Chip Multiprocessors. ISCA 2006: 339-351 - [c2]Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian:
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. ISPASS 2006: 100-111 - 2005
- [c1]Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy:
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. HPCA 2005: 28-39
Coauthor Index
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