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Hillery C. Hunter
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- affiliation: IBM TJ Watson Research Center, Yorktown Heights, NY, USA
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2020 – today
- 2020
- [j10]Saravanan Sethuraman
, Venkata Kalyan Tavva
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4635-4644 (2020)
2010 – 2019
- 2019
- [j9]Minsik Cho, Ulrich Finkler, Mauricio J. Serrano, David S. Kung, Hillery C. Hunter:
BlueConnect: Decomposing all-reduce for deep learning on heterogeneous network hierarchy. IBM J. Res. Dev. 63(6): 1:1-1:11 (2019) - [c10]Minsik Cho, Ulrich Finkler, David S. Kung, Hillery C. Hunter:
BlueConnect: Decomposing All-Reduce for Deep Learning on Heterogeneous Network Hierarchy. SysML 2019 - [e2]Srilatha Bobbie Manne, Hillery C. Hunter, Erik R. Altman:
Proceedings of the 46th International Symposium on Computer Architecture, ISCA 2019, Phoenix, AZ, USA, June 22-26, 2019. ACM 2019, ISBN 978-1-4503-6669-4 [contents] - 2018
- [c9]Grigori Fursin, Thierry Moreau, Hillery C. Hunter, Yiran Chen, Charles Qi, Tianqi Chen:
PANEL: Open panel and discussion on tackling complexity, reproducibility and tech transfer challenges in a rapidly evolving AI/ML/systems research. ReQuEST@ASPLOS 2018: 7 - 2017
- [e1]Hillery C. Hunter, Jaime Moreno, Joel S. Emer, Daniel Sánchez:
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017. ACM 2017, ISBN 978-1-4503-4952-9 [contents] - 2015
- [j8]Saibal Mukhopadhyay, Swarup Bhunia
Guest Editorial Computing in Emerging Technologies (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 5(1): 1-4 (2015) - 2014
- [j7]Hillery C. Hunter, Luis Alfonso Lastras-Montaño, Bishwaranjan Bhattacharjee:
Adapting Server Systems for New Memory Technologies. Computer 47(9): 78-84 (2014) - [j6]Saibal Mukhopadhyay, Swarup Bhunia
Guest Editorial Computing in Emerging Technologies (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 377-379 (2014) - 2013
- [c8]Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ISCA 2013: 48-59 - 2011
- [j5]Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John:
Coordinating DRAM and Last-Level-Cache Policies with the Virtual Write Queue. IEEE Micro 31(1): 90-98 (2011) - 2010
- [c7]Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John:
The virtual write queue: coordinating DRAM and last-level cache policies. ISCA 2010: 72-82 - [c6]Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John:
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory. MICRO 2010: 375-384
2000 – 2009
- 2009
- [j4]Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer:
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS. IEEE J. Solid State Circuits 44(4): 1216-1226 (2009) - [j3]Hillery C. Hunter, Erik M. Nystrom, Daniel A. Connors, Wen-mei W. Hwu:
Hardware-compiler co-design for adjustable data power savings. Microprocess. Microsystems 33(4): 244-253 (2009) - 2008
- [j2]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier. IEEE J. Solid State Circuits 43(1): 86-95 (2008) - 2007
- [c5]John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. ISSCC 2007: 486-617 - 2004
- [b1]Hillery C. Hunter:
Matching on -Chip Data Storage to Telecommunication and Media Application Properties. University of Illinois Urbana-Champaign, USA, 2004 - 2003
- [j1]Jaime H. Moreno, Victor V. Zyuban, Uzi Shvadron, Fredy D. Neeser, Jeff H. Derby, Malcolm S. Ware, Krishnan Kailas, Ayal Zaks, Amir B. Geva, Shay Ben-David, Sameh W. Asaad, Thomas W. Fox, Daniel Littrell, Marina Biberstein, Dorit Naishlos, Hillery C. Hunter:
An innovative low-power high-performance programmable signal processor for digital communications. IBM J. Res. Dev. 47(2-3): 299-326 (2003) - [c4]Hillery C. Hunter, Jaime H. Moreno:
A new look at exploiting data parallelism in embedded systems. CASES 2003: 159-169 - 2002
- [c3]Hillery C. Hunter, Wen-mei W. Hwu:
Code coverage and input variability: effects on architecture and compiler research. CASES 2002: 79-87 - 2001
- [c2]John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu:
Enhancing loop buffering of media and telecommunications applications using low-overhead predication. MICRO 2001: 262-273 - 2000
- [c1]Daniel A. Connors, Hillery C. Hunter, Ben-Chung Cheng, Wen-mei W. Hwu:
Hardware Support for Dynamic Management of Compiler-Directed Computation Reuse. ASPLOS 2000: 222-233
Coauthor Index
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