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Sushanta K. Mandal
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2010 – 2019
- 2010
- [c4]Abhishek Pathak, Sushanta K. Mandal, Raj Kumar Nagpal, Rakesh Malik:
Modelling of Power Distribution Network and Decoupling Network Design for High Speed VLSI Design. DELTA 2010: 194- - [c3]Arunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal:
A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process. VLSI Design 2010: 312-317
2000 – 2009
- 2008
- [j1]Sushanta K. Mandal, Shamik Sural, Amit Patra:
ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 188-192 (2008) - 2006
- [c2]Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural:
A Wide-Band Lumped Element Compact CAD Model of Si-Based Planar Spiral Inductor for RFIC Design. VLSI Design 2006: 619-624 - 2005
- [c1]Sushanta K. Mandal, Arijit De, Amit Patra, Shamik Sural:
A simple wide-band compact model and parameter extraction using particle swarm optimization of on-chip spiral inductors for silicon RFICs. ACM Great Lakes Symposium on VLSI 2005: 168-171
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last updated on 2024-04-25 05:59 CEST by the dblp team
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