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Thomas Ilsche
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2020 – today
- 2024
- [c38]Thomas Ilsche, Sebastian Schräder, Robert Schöne:
Optimizing Idle Power of HPC Systems: Practical Insights and Methods. CLUSTER Workshops 2024: 19-25 - [c37]Hannes Tröpgen, Robert Schöne, Thomas Ilsche, Daniel Hackenberg:
16 Years of SPEC Power: An Analysis of x86 Energy Efficiency Trends. CLUSTER Workshops 2024: 76-80 - [c36]Lukas Alt
, Anara Kozhokanova
An Experimental Setup to Evaluate RAPL Energy Counters for Heterogeneous Memory. ICPE 2024: 71-82 - [c35]Robert Schöne
Energy Efficiency Features of the Intel Alder Lake Architecture. ICPE 2024: 95-106 - [i7]Francieli Boito, Jim M. Brandt, Valeria Cardellini
Autonomy Loops for Monitoring, Operational Data Analytics, Feedback, and Response in HPC Operations. CoRR abs/2401.16971 (2024) - 2023
- [c34]Francieli Boito, Jim M. Brandt, Valeria Cardellini
Autonomy Loops for Monitoring, Operational Data Analytics, Feedback, and Response in HPC Operations. CLUSTER Workshops 2023: 37-43 - [c33]Jonas H. Müller Korndörfer
How Do OS and Application Schedulers Interact? An Investigation with Multithreaded Applications. Euro-Par 2023: 214-228 - [c32]Hannes Tröpgen
Evaluating the Energy Measurements of the IBM POWER9 On-Chip Controller. ICPE 2023: 67-76 - [i6]Hannes Tröpgen, Mario Bielert, Thomas Ilsche:
Evaluating the Energy Measurements of the IBM POWER9 On-Chip Controller. CoRR abs/2304.12646 (2023) - 2022
- [c31]Thomas Ilsche, Mario Bielert, Christian von Elm
Bridging the Gap between Application Performance Analysis and System Monitoring. CLUSTER 2022: 611-615 - [c30]Markus Velten
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. ICPE 2022: 165-175 - [i5]Markus Velten, Robert Schöne, Thomas Ilsche, Daniel Hackenberg:
Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. CoRR abs/2204.03290 (2022) - 2021
- [c29]Robert Schöne
Energy Efficiency Aspects of the AMD Zen 2 Architecture. CLUSTER 2021: 562-571 - [c28]Christian von Elm
Investigating the Cause and Effect of an AMD Zen Energy Management Anomaly. ICPE (Companion) 2021: 103-106 - [i4]Robert Schöne, Thomas Ilsche, Mario Bielert, Markus Velten, Markus Schmidl, Daniel Hackenberg:
Energy Efficiency Aspects of the AMD Zen 2 Architecture. CoRR abs/2108.00808 (2021) - 2020
- [b1]Thomas Ilsche:
Energy Measurements of High Performance Computing Systems: From Instrumentation to Analysis. Dresden University of Technology, Germany, 2020
2010 – 2019
- 2019
- [j3]Thomas Ilsche, Robert Schöne, Joseph Schuchart, Daniel Hackenberg
Power measurement techniques for energy-efficient computing: reconciling scalability, resolution, and accuracy. SICS Softw.-Intensive Cyber Phys. Syst. 34(1): 45-52 (2019) - [c27]Robert Schöne
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. HPCS 2019: 399-406 - [c26]Thomas Ilsche, Daniel Hackenberg
MetricQ: A Scalable Infrastructure for Processing High-Resolution Time Series Data. DAAC@SC 2019: 7-12 - [i3]Robert Schöne, Thomas Ilsche, Mario Bielert, Andreas Gocht
Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. CoRR abs/1905.12468 (2019) - 2018
- [c25]Thomas Ilsche, Robert Schöne
System Monitoring with lo2s: Power and Runtime Impact of C-State Transitions. IPDPS Workshops 2018: 712-715 - [i2]Ronny Brendel, Bert Wesarg, Ronny Tschüter, Matthias Weber, Thomas Ilsche, Sebastian Oeste:
Generic Library Interception for Improved Performance Measurement and Insight. CoRR abs/1803.07495 (2018) - [i1]Joseph Schuchart, Daniel Hackenberg, Robert Schöne, Thomas Ilsche, Ramkumar Nagappan, Michael K. Patterson:
The Shift from Processor Power Consumption to Performance Variations: Fundamental Implications at Scale. CoRR abs/1808.08106 (2018) - 2017
- [c24]Thomas Ilsche, Robert Schöne
lo2s - Multi-core System and Application Performance Analysis for Linux. CLUSTER 2017: 801-804 - [c23]Thomas Ilsche, Marcus Hähnel, Robert Schöne
Powernightmares: The Challenge of Efficiently Using Sleep States on Multi-core Systems. Euro-Par Workshops 2017: 623-635 - [c22]Richard Grunzke, Maximilian Neumann, Thomas Ilsche, Volker Hartmann
Design Evaluation of a Performance Analysis Trace Repository. ICCS 2017: 2190-2199 - [c21]Bho Matthiesen
Secure and energy-efficient interconnects for board-to-board communication. ICUWB 2017: 1-7 - [c20]Mohak Chadha, Thomas Ilsche, Mario Bielert, Wolfgang E. Nagel:
A Statistical Approach to Power Estimation for x86 Processors. IPDPS Workshops 2017: 1012-1019 - [c19]Ronny Brendel, Bert Wesarg, Ronny Tschüter, Matthias Weber, Thomas Ilsche, Sebastian Oeste:
Generic Library Interception for Improved Performance Measurement and Insight. ESPT/VPA@SC 2017: 21-37 - [c18]Till Smejkal, Marcus Hähnel, Thomas Ilsche, Michael Roitzsch, Wolfgang E. Nagel, Hermann Härtig:
E-Team: Practical Energy Accounting for Multi-Core Systems. USENIX ATC 2017: 589-601 - 2016
- [j2]Joseph Schuchart, Daniel Hackenberg
The shift from processor power consumption to performance variations: fundamental implications at scale. Comput. Sci. Res. Dev. 31(4): 197-205 (2016) - [c17]Robert Schöne, Thomas Ilsche, Mario Bielert, Daniel Molka, Daniel Hackenberg:
Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors. E2SC@SC 2016: 69-76 - [c16]Stefan Pfennig, Kim Feldhoff, Florina M. Ciorba, Elke Franz, Tobias Reiher, Mario Bielert, Thomas Ilsche, Wolfgang E. Nagel:
Simulation models verification for resilient communication on a highly adaptive energy-efficient computer. SpringSim (HPS) 2016: 6 - 2015
- [c15]Thomas Ilsche, Daniel Hackenberg
Power measurements for compute nodes: Improving sampling rates, granularity and accuracy. IGSC 2015: 1-8 - [c14]Daniel Hackenberg
An Energy Efficiency Feature Survey of the Intel Haswell Processor. IPDPS Workshops 2015: 896-904 - [c13]Mario Bielert, Florina M. Ciorba
HAEC-SIM: a simulation framework for highly adaptive energy-efficient computing platforms. SimuTools 2015: 129-138 - 2014
- [j1]Thomas Ilsche, Joseph Schuchart, Jason Cope, Dries Kimpe, Terry R. Jones
Optimizing I/O forwarding techniques for extreme-scale event tracing. Clust. Comput. 17(1): 1-18 (2014) - [c12]Iraklis Psaroudakis, Thomas Kissinger, Danica Porobic
Dynamic fine-grained scheduling for energy-efficient main-memory queries. DaMoN 2014: 1:1-1:7 - [c11]Florina M. Ciorba, Thomas Ilsche, Elke Franz, Stefan Pfennig, Christian Scheunert, Ulf Markwardt, Joseph Schuchart, Daniel Hackenberg
Analysis of Parallel Applications on a High Performance-Low Energy Computer. Euro-Par Workshops (2) 2014: 474-485 - [c10]Stefan Pfennig, Elke Franz, Florina M. Ciorba
Modeling communication delays for network coding and routing for error-prone transmission. FGCT 2014: 19-24 - [c9]Sebastian Oeste, Andreas Knüpfer, Thomas Ilsche:
Towards Parallel Performance Analysis Tools for the OpenSHMEM Standard. OpenSHMEM 2014: 90-104 - [c8]Sebastian Götz, Thomas Ilsche, Jorge Cardoso, Josef Spillner, Uwe Aßmann
Energy-Efficient Data Processing at Sweet Spot Frequencies. OTM Workshops 2014: 154-171 - [c7]Daniel Hackenberg
HDEEM: high definition energy efficiency monitoring. E2SC@SC 2014: 1-10 - [c6]Sebastian Götz, Thomas Ilsche, Jorge Cardoso
Energy-Efficient Databases Using Sweet Spot Frequencies. UCC 2014: 871-876 - 2013
- [c5]Daniel Hackenberg
Power measurement techniques on standard compute nodes: A quantitative comparison. ISPASS 2013: 194-204 - 2012
- [c4]Thomas Ilsche, Joseph Schuchart, Jason Cope, Dries Kimpe, Terry R. Jones
Enabling event tracing at leadership-class scale through I/O forwarding middleware. HPDC 2012: 49-60 - [c3]Christos Kartsaklis, Oscar R. Hernandez, Chung-Hsing Hsu, Thomas Ilsche, Wayne Joubert, Richard L. Graham:
HERCULES: A Pattern Driven Code Transformation System. IPDPS Workshops 2012: 574-583 - 2010
- [c2]Robert Schöne
The VampirTrace Plugin Counter Interface: Introduction and Examples. Euro-Par Workshops 2010: 501-511 - [c1]Robert Dietrich, Thomas Ilsche, Guido Juckeland
Non-intrusive Performance Analysis of Parallel Hardware Accelerated Applications on Hybrid Architectures. ICPP Workshops 2010: 135-143
Coauthor Index
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