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Steffen Rülke
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2010 – 2019
- 2012
- [c22]Thilo Vörtler, Steffen Rülke, Petra Hofstedt:
Bounded model checking of Contiki applications. DDECS 2012: 258-261
2000 – 2009
- 2009
- [j1]Frank Rogin, Thomas Klotz, Görschwin Fey
, Rolf Drechsler
Advanced verification by automatic property generation. IET Comput. Digit. Tech. 3(4): 338-353 (2009) - [c21]Frank Rogin, Rolf Drechsler
Automatic debugging of System-on-a-Chip designs. SoCC 2009: 333-336 - 2008
- [c20]Frank Rogin, Thomas Klotz, Görschwin Fey
Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548 - [c19]Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke:
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. ISVLSI 2008: 298-303 - 2007
- [c18]Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt:
A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. DSD 2007: 147-150 - [c17]Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke:
An Integrated SystemC Debugging Environment. FDL 2007: 140-145 - [c16]Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker:
High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS 2007: 1-8 - [c15]Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt:
A Tailored Design Partitioning Method for Hardware Emulation. IEEE International Workshop on Rapid System Prototyping 2007: 99-105 - 2006
- [c14]Frank Rogin, Erhard Fehlauer, Steffen Rülke, Sebastian Ohnewald, Thomas Berndt:
Non-Intrusive High-level SystemC Debugging. FDL 2006: 155-161 - [c13]Maik Boden, Steffen Rülke, Jürgen Becker:
A high-level target-precise model for designing reconfigurable HW tasks. IPDPS 2006 - 2005
- [c12]Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger:
A Low-Cost Realization of an Adaptable Protocol Processing Unit. IPDPS 2005 - 2004
- [c11]Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke:
Cost-Efficient Implementation of Adaptive Finite State Machines. DSD 2004: 144-151 - [c10]Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki:
IPQ: IP Qualification for Efficient System Design. ISQED 2004: 478-482 - [c9]Jörg Schneider, Vincent Kotzsch, Steffen Rülke:
Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. PARELEC 2004: 177-180 - 2002
- [c8]Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke:
Enhanced Reusability for SoC-Based HW/SW Co-Design. DSD 2002: 94-101 - [c7]Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig:
Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. DSD 2002: 364-370 - [c6]Jörg Schneider, Maik Boden, Steffen Rülke:
Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. MBMV 2002: 36-45 - 2001
- [c5]Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo:
Two-Criterial Constraint-Driven FSM State Encoding for Low Power. DSD 2001: 94-101
1990 – 1999
- 1998
- [c4]Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske:
Multi-Criterial State Assignment for Low Power FSM Design. EUROMICRO 1998: 10261-10268 - [c3]Klaus Feske, Steffen Rülke, Manfred Koegst:
FPGA based prototyping using a target driven FSM partitioning strategy. ICECS 1998: 89-92 - [c2]Manfred Koegst, Günter Franke, Klaus Feske, Steffen Rülke:
Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung. MBMV 1998: 30-37 - 1997
- [c1]Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske:
Low Power Design of FSMs by State Assignment and Disabling Self-Loops. EUROMICRO 1997: 323-330 - 1990
- [b1]Steffen Rülke:
EASY - ein Werkzeug zur Unterstützung der automatischen High-Level-Synthese des Datenteils digitaler Systeme: Konzeption und Implementierung einer Experimentalversion. Academy of Sciences of the German Democratic Republic, Berlin, Germany, 1990
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