default search action
Reza Sedaghat
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2022
- [j22]Prathap Siddavaatam, Reza Sedaghat, Nahid Sahelgozin:
A Novel Machine Learning Framework for Covid-19 Image Classification with Bio-heuristic Optimization. Trans. Comput. Sci. 39: 85-108 (2022) - 2021
- [j21]Prathap Siddavaatam, Reza Sedaghat:
A New Bio-heuristic Hybrid Optimization for Constrained Continuous Problems. Trans. Comput. Sci. 38: 76-97 (2021) - [j20]Noel Jose Thengappurackal Laiju, Reza Sedaghat, Prathap Siddavaatam:
Novel Hybrid GWO-WOA and BAT-PSO Algorithms for Solving Design Optimization Problems. Trans. Comput. Sci. 38: 113-144 (2021)
2010 – 2019
- 2019
- [j19]Prathap Siddavaatam, Reza Sedaghat:
A New Adaptive Security Architecture with Extensible Computation Complexity for Generic Ciphers. J. Hardw. Syst. Secur. 3(4): 319-337 (2019) - [j18]Prathap Siddavaatam, Reza Sedaghat:
Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis. Swarm Evol. Comput. 49: 44-61 (2019) - 2018
- [j17]Prathap Siddavaatam, Reza Sedaghat:
A Delta-Diagram Based Synthesis for Cross Layer Optimization Modeling of IoT. Trans. Comput. Sci. 33: 1-24 (2018) - 2017
- [c13]Prathap Siddavaatam, Reza Sedaghat, Aakriti Tarun Sharma:
intel-LEACH: An optimal framework for node selection using dynamic clustering for wireless sensor networks. ICITST 2017: 359-364 - 2016
- [c12]Prathap Siddavaatam, Reza Sedaghat, Min Hsuan Cheng:
An adaptive security framework with extensible computational complexity for cipher systems. ICITST 2016: 133-140 - [c11]Min Hsuan Cheng, Reza Sedaghat, Prathap Siddavaatam:
A New Adaptable Construction of Modulo Addition with Scalable Security for Stream Ciphers. NSS 2016: 383-397 - 2015
- [j16]Anirban Sengupta, Reza Sedaghat:
Swarm intelligence driven design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis based on user power-delay budget. Microelectron. Reliab. 55(6): 990-1004 (2015) - [j15]Behnaz Abdoli, Reza Sedaghat, Manuchehr Taghiloo:
Optimized Predictive Zonal Search (OPZS) for block-based motion estimation. Signal Process. Image Commun. 39: 293-304 (2015) - [c10]Anirban Sengupta, Reza Sedaghat:
Exploration of optimal multi-cycle transient fault secured datapath during high level synthesis based on user area-delay budget. CCECE 2015: 69-74 - 2012
- [j14]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
:
Rapid exploration of integrated scheduling and module selection in high level synthesis for application specific processor design. Microprocess. Microsystems 36(4): 303-314 (2012) - [j13]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
A multi structure genetic algorithm for integrated design space exploration of scheduling and allocation in high level synthesis for DSP kernels. Swarm Evol. Comput. 7: 35-46 (2012) - 2011
- [j12]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP). Microprocess. Microsystems 35(4): 392-404 (2011) - [j11]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems. Microelectron. Reliab. 51(2): 502-512 (2011) - [j10]Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe:
Switch-level emulation of strength-base soft error detection. Microelectron. Reliab. 51(3): 692-702 (2011) - [c9]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Integrated design space exploration based on power-performance trade-off using genetic algorithm. ACAI 2011: 77-81 - [c8]Pallabi Sarkar
Application specific processor vs. microblaze soft core RISC processor: FPGA based performance and CPR analysis. ACAI 2011: 82-85 - [c7]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Integrated scheduling, allocation and binding in High Level Synthesis for performance-area tradeoff of digital media applications. CCECE 2011: 533-537 - [c6]Anirban Sengupta, Reza Sedaghat, Pallabi Sarkar
Priority function based power efficient rapid Design Space Exploration of scheduling and module selection in high level synthesis. CCECE 2011: 538-543 - [c5]Anirban Sengupta, Reza Sedaghat:
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration. ISQED 2011: 486-494 - 2010
- [j9]Reza Sedaghat, M. Reza Javaheri, Prabhleen K. Kalkat, Jalal Mohammad Chikhe:
Switch-level soft error emulation for SET-induced pulses of variable strengths. Microelectron. J. 41(10): 651-661 (2010) - [j8]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective. Microelectron. Reliab. 50(3): 424-437 (2010) - [j7]M. Reza Javaheri, Reza Sedaghat:
Strength violation effect on soft-error detection in sub-micron technology. Microelectron. Reliab. 50(7): 971-977 (2010) - [c4]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Rapid design space exploration for multi parametric optimization of VLSI designs. ISCAS 2010: 3164-3167 - [c3]Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta:
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures. ISCAS 2010: 3176-3179
2000 – 2009
- 2009
- [j6]M. Reza Javaheri, Reza Sedaghat:
Multi-valued logic mapping of resistive short and open delay-fault testing in deep sub-micron technologies. Microelectron. Reliab. 49(2): 178-185 (2009) - 2008
- [j5]Peter Ming-Han Lee, Reza Sedaghat:
FPGA-based switch-level fault emulation using module-based dynamic partial reconfiguration. Microelectron. Reliab. 48(10): 1724-1733 (2008) - [c2]M. Reza Javaheri, Reza Sedaghat:
A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies. CSICC 2008: 653-660 - 2007
- [j4]Mayuri Kunchwar, Reza Sedaghat, Vadim Geurkov
Dynamic behavior of resistive faults in nanometer technology. Microelectron. Reliab. 47(12): 2141-2146 (2007) - 2006
- [j3]Hyunsuk Moon, Reza Sedaghat:
FPGA-Based adaptive digital predistortion for radio-over-fiber links. Microprocess. Microsystems 30(3): 145-154 (2006) - [j2]M. Reza Javaheri, Reza Sedaghat, Leo Kant, Jason Zalev:
Verification and fault synthesis algorithm at switch-level. Microprocess. Microsystems 30(4): 199-208 (2006) - [j1]Reza Sedaghat, Mayuri Kunchwar, Raha Abedi, M. Reza Javaheri:
Transistor-level to gate-level comprehensive fault synthesis for n-input primitive gates. Microelectron. Reliab. 46(12): 2149-2158 (2006) - 2003
- [c1]Reza Sedaghat:
A fast algorithm to reduce 2-dimensional assignment problems to 1-dimensional assignment problems for FPGA-based fault simulation. ISCAS (5) 2003: 213-216
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:25 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: