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Chang-Ming Lai
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2020 – today
- 2020
- [c11]Eric Lu, Wen-Kai Li, Zhiming Deng, Edris Rostami, Pi-An Wu, Keng-Meng Chang, Yu-Chen Chuang, Chang-Ming Lai, Yang-Chuan Chen, Tzu-Hsuin Peng, Tzung-Chuen Tsai, Hui-Hsien Liu, Chien-Chih Chiu, Bryan Huang, Yao-Chi Wang, Jing-Hong Conan Zhan, Osama Shana'a:
10.4 A 4×4 Dual-Band Dual-Concurrent WiFi 802.11ax Transceiver with Integrated LNA, PA and T/R Switch Achieving +20dBm 1024-QAM MCS11 Pout and -43dB EVM Floor in 55nm CMOS. ISSCC 2020: 178-180
2010 – 2019
- 2015
- [j3]Jen-Huan Tsai, Hui-Huan Wang, Yang-Chi Yen, Chang-Ming Lai, Yen-Ju Chen, Po-Chiun Huang, Ping-Hsuan Hsieh, Hsin Chen, Chao-Cheng Lee:
A 0.003 mm2 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching. IEEE J. Solid State Circuits 50(6): 1382-1398 (2015) - 2014
- [j2]Chang-Ming Lai, Kai-Wen Tan, Yen-Ju Chen, Ta-Shun Chu:
A UWB Impulse-Radio Timed-Array Radar With Time-Shifted Direct-Sampling Architecture in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2074-2087 (2014) - [c10]Chin-Fu Li, Shih-Chieh Chou, Chang-Ming Lai, Cuei-Ling Hsieh, Jenny Yi-Chun Liu, Po-Chiun Huang:
A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer. A-SSCC 2014: 337-340 - [c9]Yu-Hsien Kao, Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ping-Hsuan Hsieh, Ta-Shun Chu:
28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS. ISSCC 2014: 474-475 - [c8]Cuei-Ling Hsieh, Chang-Ming Lai, Guan-Hong Ke, Jenny Yi-Chun Liu, Po-Chiun Huang:
A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver. VLSI-DAT 2014: 1-4 - 2013
- [c7]Chang-Ming Lai, Jen-Ming Wu, Po-Chiun Huang, Ta-Shun Chu:
A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS. ISSCC 2013: 242-243 - [c6]Chang-Ming Lai, Yi-Chung Chen, Po-Chiun Huang:
Time-domain analog-to-digital converters with domino delay lines. VLSI-DAT 2013: 1-4 - 2012
- [c5]Chang-Ming Lai, Kai-Wen Tan, Liu-Yuan Yu, Yen-Ju Chen, Jun-Wei Huang, Shr-Chau Lai, Feng-Hsu Chung, Chia-Fung Yen, Jen-Ming Wu, Po-Chiun Huang, Keh-Jeng Chang, Shi-Yu Huang, Ta-Shun Chu:
A UWB IR timed-array radar using time-shifted direct-sampling architecture. VLSIC 2012: 54-55 - 2011
- [c4]Chang-Ming Lai, Meng-Hung Shen, Geng-Yi Pan, Po-Chiun Huang:
A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection. A-SSCC 2011: 357-360 - [c3]Chang-Ming Lai, Meng-Hung Shen, Yi-Da Wu, Kai-Hsiang Huang, Po-Chiun Huang:
A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS. ISCAS 2011: 981-984 - [c2]Chin-Fu Li, Chang-Ming Lai, Ping-Chuan Chiang, Po-Chiun Huang:
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension. ISOCC 2011: 120-123 - 2010
- [j1]Yi-Da Wu, Chang-Ming Lai, Chao-Cheng Lee, Po-Chiun Huang:
A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer. IEEE J. Solid State Circuits 45(11): 2283-2291 (2010)
2000 – 2009
- 2006
- [c1]Yi-Da Wu, Chang-Ming Lai, Chih-Yuan Chou, Po-Chiun Huang:
An OPLL-DDS based frequency synthesizer for DCS-1800 receiver. ISCAS 2006
Coauthor Index
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