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Dong-Ryeol Oh
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2020 – today
- 2024
- [j7]Jae-Hyun Chung
, Ye-Dam Kim
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. IEEE J. Solid State Circuits 59(8): 2481-2491 (2024) - 2022
- [j6]Dong-Ryeol Oh
A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. IEEE J. Solid State Circuits 57(9): 2791-2801 (2022) - [c3]Kyoung-Jun Moon, Dong-Ryeol Oh
A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET. VLSI Technology and Circuits 2022: 172-173 - 2021
- [j5]Dong-Ryeol Oh
An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. IEEE J. Solid State Circuits 56(4): 1216-1226 (2021) - 2020
- [j4]Kyoung-Jun Moon
A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. IEEE Trans. Circuits Syst. 67-II(12): 2843-2847 (2020) - [c2]Dong-Ryeol Oh
An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j3]Dong-Ryeol Oh
A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $\times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. IEEE J. Solid State Circuits 54(1): 288-297 (2019) - 2015
- [j2]Jong-In Kim, Dong-Ryeol Oh
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. IEEE J. Solid State Circuits 50(10): 2319-2330 (2015) - [c1]Dong-Ryeol Oh
A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. ESSCIRC 2015: 323-326
2000 – 2009
- 2008
- [j1]Byeong-Seok Shin, Dong-Ryeol Oh, Daniel Kang:
Real-Time Point-Based Rendering Using Visibility Map. IEICE Trans. Inf. Syst. 91-D(1): 124-131 (2008)
Coauthor Index
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