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Kyuseung Han
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2020 – today
- 2024
- [j12]Eunjin Choi, Jina Park, Kyeongwon Lee
, Jae-Jin Lee, Kyuseung Han, Woojoo Lee
Day-Night architecture: Development of an ultra-low power RISC-V processor for wearable anomaly detection. J. Syst. Archit. 152: 103161 (2024) - [j11]Jina Park, Kyuseung Han
Designing Low-Power RISC-V Multicore Processors With a Shared Lightweight Floating Point Unit for IoT Endnodes. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4106-4119 (2024) - [c15]Hyeonguk Jang, Jae-Jin Lee, Kyuseung Han:
Optimizing Implementation of SNN for Embedded System. ICACT 2024: 104-106 - [c14]Kyuseung Han
STARC: Crafting Low-Power Mixed-Signal Neuromorphic Processors by Bridging SNN Frameworks and Analog Designs. ISLPED 2024: 1-6 - 2023
- [c13]Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee:
Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. DATE 2023: 1-2 - [c12]Jina Park, Kyuseung Han, Eunjin Choi, Sukho Lee, Jae-Jin Lee, Woojoo Lee, Massoud Pedram:
Florian: Developing a Low-Power RISC-V Multicore Processor with a Shared Lightweight FPU. ISLPED 2023: 1-6 - 2022
- [c11]Hyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han:
Releasing the Memory Bottleneck to Display Video Correctly. ISOCC 2022: 340-341 - 2021
- [j10]Hyeonguk Jang
Developing a Multicore Platform Utilizing Open RISC-V Cores. IEEE Access 9: 120010-120023 (2021) - [j9]Kyuseung Han
Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End Nodes. IEEE Internet Things J. 8(6): 4642-4656 (2021) - [c10]Wooyoung Lee, Jina Park, Changjun Byun, Eunjin Choi, Jae-Hyoung Lee, Woojoo Lee, Kyung Jin Byun, Kyuseung Han:
K-means Clustering-specific Lightweight RISC-V processor. ISOCC 2021: 391-392
2010 – 2019
- 2019
- [j8]Hyeonguk Jang, Kyuseung Han
MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems. IEEE Access 7: 80011-80019 (2019) - [j7]Kyuseung Han
A Diagnosable Network-on-Chip for FPGA Verification of Intellectual Properties. IEEE Des. Test 36(2): 81-87 (2019) - [j6]Woojoo Lee
TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1758-1770 (2019) - [c9]Kyuseung Han
TIP: A Temperature Effect Inversion-Aware Ultra-Low Power System-on-Chip Platform. ISLPED 2019: 1-6 - [c8]Hyeonguk Jang, Kyuseung Han, Sukho Lee, Jae-Jin Lee:
Supporting Serial Interfaces on Virtual SoC Platforms to Develop Sensor Applications. ISOCC 2019: 101-102 - 2018
- [j5]Kyuseung Han, Jae-Jin Lee, Jinho Lee
TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature Effect Inversion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(2): 458-471 (2018) - 2017
- [j4]Woojoo Lee, Kyuseung Han, Yanzhi Wang, Tiansong Cui, Shahin Nazarian, Massoud Pedram:
TEI-power: Temperature Effect Inversion-Aware Dynamic Thermal Management. ACM Trans. Design Autom. Electr. Syst. 22(3): 51:1-51:25 (2017) - 2014
- [j3]Manhwee Jo, Dongwook Lee, Kyuseung Han, Kiyoung Choi:
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study. Integr. 47(2): 232-241 (2014) - [j2]Kyuseung Han, Ganghee Lee, Kiyoung Choi:
Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable Architecture. IEEE Trans. Dependable Secur. Comput. 11(4): 392-398 (2014) - [c7]Jihyun Ryoo, Kyuseung Han, Kiyoung Choi:
Leveraging parallelism in the presence of control flow on CGRAs. ASP-DAC 2014: 285-291 - 2013
- [j1]Kyuseung Han, Junwhan Ahn, Kiyoung Choi:
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. ACM Trans. Archit. Code Optim. 10(2): 8:1-8:25 (2013) - [c6]Kyuseung Han, Kiyoung Choi, Jongeun Lee:
Compiling control-intensive loops for CGRAs with state-based full predication. DATE 2013: 1579-1582 - [c5]Manhwee Jo, Kyuseung Han, Kiyoung Choi:
Enhancing Utilization of Integer Functional Units for High-Throughput Floating Point Operations on Coarse-Grained Reconfigurable Architecture. MUE 2013: 1161-1167 - 2012
- [c4]Kyuseung Han, Seongsik Park, Kiyoung Choi:
State-based full predication for low power coarse-grained reconfigurable architecture. DATE 2012: 1367-1372 - 2011
- [c3]Yangsu Kim, Kyuseung Han, Kiyoung Choi:
A host-accelerator communication architecture design for efficient binary acceleration. ISOCC 2011: 361-364 - 2010
- [c2]Kyuseung Han, Jong Kyung Paek, Kiyoung Choi:
Acceleration of control flow on CGRA using advanced predicated execution. FPT 2010: 429-432
2000 – 2009
- 2009
- [c1]Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, Kiwook Yoon:
Coarse-grained reconfigurable architecture for multiple application domains: a case study. ICHIT 2009: 546-553
Coauthor Index
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