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Petr Fiser
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2020 – today
- 2024
- [c48]Jan Schmidt
, Petr Fiser
A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks. DDECS 2024: 86-91 - [c47]Jan Schmidt
Adaptive Input Normalization for Quantized Neural Networks. DDECS 2024: 130-135 - [c46]Subrata Das, Arighna Deb, Petr Fiser, Debesh Kumar Das:
Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. DSD 2024: 11-18 - [i1]Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek, Petr Fiser, Frantisek Steiner, Tomás Blecha, Peter Langendörfer, Ievgen Kabin:
On the Influence of the Laser Illumination on the Logic Cells Current Consumption. CoRR abs/2407.06758 (2024) - 2023
- [c45]Robert Hülle, Petr Fiser, Jan Schmidt:
Reducing Output Response Aliasing Using Boolean Optimization Techniques. DDECS 2023: 33-38 - [c44]Dmytro Petryk, Zoya Dyka, Milos Krstic, Jan Belohoubek
On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results. ICECS 2023: 1-6 - [c43]Subrata Das, Arighna Deb, Petr Fiser:
Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring. ISDCS 2023: 1-6 - 2022
- [c42]Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola
A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. DDECS 2022: 38-43 - 2021
- [c41]Alberto Bosio, Mayeul Cantan
Emerging Technologies: Challenges and Opportunities for Logic Synthesis. DDECS 2021: 93-98 - [c40]Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das:
Minimization of Switching Activity of Graphene Based Circuits. VLSID 2021: 139-144 - 2020
- [j12]Martin Novotný
Special issue on DSD 2018. Microprocess. Microsystems 77: 103204 (2020) - [c39]Jan Belohoubek
Standard Cell Tuning Enables Data-Independent Static Power Consumption. DDECS 2020: 1-6 - [c38]Jaroslav Borecký, Robert Hülle, Petr Fiser:
Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. DSD 2020: 684-691
2010 – 2019
- 2019
- [j11]Petr Fiser
SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support. J. Circuits Syst. Comput. 28(Supplement-1): 1940010:1-1940010:29 (2019) - [c37]Jan Belohoubek
Using Voters May Lead to Secret Leakage. DDECS 2019: 1-4 - [c36]Jan Belohoubek, Petr Fiser, Jan Schmidt:
CMOS Illumination Discloses Processed Data. DSD 2019: 381-388 - 2018
- [j10]Robert Hülle, Petr Fiser
ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction. Microprocess. Microsystems 61: 43-57 (2018) - [j9]Ivo Hálecek
Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR. Microelectron. Reliab. 81: 274-286 (2018) - [c35]Umberto Ferrandino, Marcello Traiola
Synthesis of Finite State Machines on Memristor Crossbars. DDECS 2018: 107-112 - [c34]Petr Fiser, Václav Simek
Optimum polymorphic circuits synthesis method. DTIS 2018: 1-6 - 2017
- [j8]Jan Belohoubek
Error masking method based on the short-duration offline test. Microprocess. Microsystems 52: 236-250 (2017) - [c33]Ivo Hálecek, Petr Fiser, Jan Schmidt:
Are XORs in logic synthesis really necessary? DDECS 2017: 134-139 - [c32]Petr Fiser, Ivo Hálecek, Jan Schmidt:
SAT-Based Generation of Optimum Function Implementations with XOR Gates. DSD 2017: 163-170 - [c31]Robert Hülle, Petr Fiser, Jan Schmidt:
SAT-Based ATPG for Zero-Aliasing Compaction. DSD 2017: 307-314 - 2016
- [c30]Róbert Tamási, Miroslav Siebert, Elena Gramatová, Petr Fiser:
A new method for path criticality calculation. DDECS 2016: 190-193 - [c29]Marek Lipovský, Ján Svarc, Elena Gramatová, Petr Fiser:
A new user-friendly ATPG platform for digital circuits. DDECS 2016: 210-213 - [c28]Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das:
A rule-based approach for minimizing power dissipation of digital circuits. DDECS 2016: 237-242 - [c27]Jan Belohoubek
Error Correction Method Based on the Short-Duration Offline Test. DSD 2016: 495-502 - 2015
- [c26]Jan Belohoubek
Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy. DSD 2015: 280-283 - 2014
- [j7]Igor Lemberski, Petr Fiser
Asynchronous sum-of-products logic minimization and orthogonalization. Int. J. Circuit Theory Appl. 42(6): 562-571 (2014) - [j6]Igor Lemberski, Petr Fiser
Dual-rail asynchronous logic multi-level implementation. Integr. 47(1): 148-159 (2014) - [j5]Jirí Balcárek, Petr Fiser, Jan Schmidt:
On don't cares in test compression. Microprocess. Microsystems 38(8): 754-765 (2014) - [c25]Petr Fiser, Jan Schmidt, Jiri Balcarek:
Sources of bias in EDA tools and its influence. DDECS 2014: 258-261 - [c24]Jan Schmidt, Petr Fiser
On Robustness of EDA Tools. DSD 2014: 427-434 - [c23]Jiri Balcarek, Petr Fiser, Jan Schmidt:
PBO-Based Test Compression. DSD 2014: 679-682 - 2013
- [j4]Jiri Balcarek, Petr Fiser
Techniques for SAT-based constrained test pattern generation. Microprocess. Microsystems 37(2): 185-195 (2013) - [j3]Jan Schmidt, Petr Fiser
The influence of implementation type on dependability parameters. Microprocess. Microsystems 37(6-7): 641-648 (2013) - [c22]Jiri Balcarek, Petr Fiser
Simulation and SAT Based ATPG for Compressed Test Generation. DSD 2013: 445-452 - 2012
- [c21]Petr Fiser, Jan Schmidt:
Improving the iterative power of resynthesis. DDECS 2012: 30-33 - [c20]Jan Schmidt, Petr Fiser, Jiri Balcarek:
The Influence of Implementation Technology on Dependability Parameters. DSD 2012: 368-373 - 2011
- [c19]Jiri Balcarek, Petr Fiser, Jan Schmidt:
Techniques for SAT-Based Constrained Test Pattern Generation. DSD 2011: 360-366 - 2010
- [c18]Petr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina:
On logic synthesis of conventionally hard to synthesize circuits using genetic programming. DDECS 2010: 346-351 - [c17]Igor Lemberski, Petr Fiser:
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. DSD 2010: 155-162 - [c16]Jiri Balcarek, Petr Fiser, Jan Schmidt:
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. DSD 2010: 805-808
2000 – 2009
- 2009
- [c15]Igor Lemberski, Petr Fiser:
Asynchronous two-level logic of reduced cost. DDECS 2009: 68-73 - [c14]Jan Schmidt, Petr Fiser
The Case for a Balanced Decomposition Process. DSD 2009: 601-604 - [c13]Petr Fiser
A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. DSD 2009: 757-764 - 2008
- [j2]Petr Fiser
Column-matching based mixed-mode test pattern generator design technique for BIST. Microprocess. Microsystems 32(5-6): 340-350 (2008) - [c12]Petr Fiser, Pemysl Rucký, Irena Vanová:
Fast Boolean Minimizer for Completely Specified Functions. DDECS 2008: 122-127 - [c11]Petr Fiser
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. DSD 2008: 96-99 - 2007
- [c10]Petr Fiser:
Pseudo-Random Pattern Generator Design for Column-Matching BIST. DSD 2007: 657-663 - 2006
- [c9]Petr Fiser, Hana Kubátová:
Multiple-Vector Column-Matching BIST Design Method. DDECS 2006: 268-273 - [c8]Petr Fiser, Hana Kubátová:
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. DSD 2006: 369-376 - [c7]Pavel Kubalík, Petr Fiser, Hana Kubátová:
Fault Tolerant System Design Method Based on Self-Checking Circuits. IOLTS 2006: 185-186 - 2004
- [c6]Petr Fiser, Hana Kubátová:
Boolean Minimizer FC-Min: Coverage Finding Process. DSD 2004: 152-159 - [c5]Petr Fiser, Hana Kubátová:
Survey of the Algorithms in the Column-Matching BIST Method. IOLTS 2004: 181 - 2003
- [j1]Jan Hlavicka, Petr Fiser:
BOOM - A Heuristic Boolean Minimizer. Comput. Artif. Intell. 22(1): 19-51 (2003) - [c4]Petr Fiser
FC-Min: A Fast Multi-Output Boolean Minimizer. DSD 2003: 451-454 - 2002
- [c3]Jan Hlavicka, Petr Fiser:
Minimization and Partitioning Method Reducing Input Sets. DELTA 2002: 434-436 - 2001
- [c2]Petr Fiser
On the Use of Mutations in Boolean Minimization. DSD 2001: 300-309 - [c1]Jan Hlavicka, Petr Fiser
BOOM - A Heuristic Boolean Minimizer. ICCAD 2001: 439-442
Coauthor Index
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last updated on 2024-11-20 20:58 CET by the dblp team
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