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Polen Kission
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Conference and Workshop Papers
- 2000
- [c9]Mohamed Benmohammed, Abdelatif Rahmoune, Polen Kission:
The application of high-level synthesis techniques for the generation of pipelined reprogrammable microcontrollers. ICECS 2000: 993-998 - 1998
- [c8]Abderrazek Jemai
, Polen Kission, Ahmed Amine Jerraya:
Architectural Simulation in the Context of Behavioral Synthesis. DATE 1998: 590-595 - 1997
- [c7]Abderrazek Jemai, Polen Kission, Ahmed Amine Jerraya:
Embedded architectural simulation within behavioral synthesis environment. ASP-DAC 1997: 227-232 - 1996
- [c6]Elisabeth Berrebi, Polen Kission, Serge Vernalde, S. De Troch, Jean-Claude Herluison, Jean Fréhel, Ahmed Amine Jerraya, Ivo Bolsens:
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. DAC 1996: 573-578 - [c5]Maher Rahmouni, Ahmed Amine Jerraya, Polen Kission, Antonio Carneiro de Mesquita Filho, Aloysio Pedroza, Luci Pirmez:
Analysis of different protocol description styles in VHDL for high-level synthesis. EURO-DAC 1996: 490-495 - 1995
- [c4]Polen Kission, Hong Ding, Ahmed Amine Jerraya:
VHDL based design methodology for hierarchy and component re-use. EURO-DAC 1995: 470-475 - 1994
- [c3]Polen Kission, Hong Ding, Ahmed Amine Jerraya:
Structured Design Methodology for High-Level Design. DAC 1994: 466-471 - [c2]Polen Kission, Hong Ding, Ahmed Amine Jerraya:
Accelerating the design process by using architectural synthesis. RSP 1994: 205-212 - 1993
- [c1]Polen Kission, Etienne Closse, Laurent Bergher, Ahmed Amine Jerraya:
Industrial experimentation of high-level synthesis. EURO-DAC 1993: 506-511
Coauthor Index
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