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Philippe Lorenzini
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2020 – today
- 2023
- [c7]Radouane Habhab
, Vincenzo Della Marca, Pascal Masson, Nadia Miridi, Clement Pribat, Simon Jeannot, Thibault Kempf, Marc Mantelli, Philippe Lorenzini, Jean-Marc Voisin, Arnaud Régnier, Stephan Niel, Francesco La Rosa:
40nm SONOS Embedded Select in Trench Memory. ESSDERC 2023: 21-24 - 2022
- [c6]Paul Devoge, Hassen Aziza, Philippe Lorenzini, Pascal Masson, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel:
A Schmitt trigger to benchmark the performance of a new zero-cost transistor. ICECS 2022 2022: 1-4 - [c5]Paul Devoge, Hassen Aziza, Philippe Lorenzini, Alexandre Malherbe, Franck Julien, Abderrezak Marzaki, Arnaud Régnier, Stephan Niel:
Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. ISCAS 2022: 761-764 - 2021
- [c4]Paul Devoge
Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. DTIS 2021: 1-5
2010 – 2019
- 2016
- [j5]Zhaopeng Wei, Gilles Jacquemod, Philippe Lorenzini, Frédéric Hameau, Emeric de Foucauld, Yves Leduc:
Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology. J. Low Power Electron. 12(1): 64-73 (2016) - 2014
- [j4]Alexandre Fonseca, Emeric de Foucauld, Philippe Lorenzini, Gilles Jacquemod:
Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop. J. Low Power Electron. 10(1): 149-162 (2014) - [c3]Alexandre Fonseca, Gilles Jacquemod, Yves Leduc, Emeric de Foucauld, Philippe Lorenzini:
VCO design in SOI technologies. NEWCAS 2014: 420-423 - 2013
- [j3]François Duhem, Fabrice Muller, Willy Aubry, Bertrand Le Gal, Daniel Négru, Philippe Lorenzini:
Design space exploration for partially reconfigurable architectures in real-time systems. J. Syst. Archit. 59(8): 571-581 (2013) - [j2]François Duhem, Nicolas Marques, Fabrice Muller, Hassan Rabah
Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. Microprocess. Microsystems 37(1): 1-8 (2013) - 2012
- [j1]François Duhem, Fabrice Muller, Philippe Lorenzini:
Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. IET Comput. Digit. Tech. 6(2): 105-113 (2012) - 2011
- [c2]François Duhem, Fabrice Muller, Philippe Lorenzini:
FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. ARC 2011: 253-260 - [c1]François Duhem
Methodology for designing partially reconfigurable systems using transaction-level modeling. DASIP 2011: 316-322
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