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Klaas Bult
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2020 – today
- 2020
- [j15]Md Shakil Akter
, Rohan Sehgal
A Resistive Degeneration Technique for Linearizing Open-Loop Amplifiers. IEEE Trans. Circuits Syst. 67-II(11): 2322-2326 (2020)
2010 – 2019
- 2018
- [j14]Md Shakil Akter
A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier. IEEE J. Solid State Circuits 53(4): 1115-1126 (2018) - [j13]Rohan Sehgal
A 13-mW 64-dB SNDR 280-MS/s Pipelined ADC Using Linearized Integrating Amplifiers. IEEE J. Solid State Circuits 53(7): 1878-1888 (2018) - [j12]Md Shakil Akter
A 66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier. IEEE J. Solid State Circuits 53(10): 2939-2950 (2018) - 2017
- [c11]Rohan Sehgal
A 13mW 64dB SNDR 280MS/s pipelined ADC using linearized open-loop class-AB amplifiers. ESSCIRC 2017: 131-134 - 2015
- [j11]Rohan Sehgal
A 12 b 53 mW 195 MS/s Pipeline ADC with 82 dB SFDR Using Split-ADC Calibration. IEEE J. Solid State Circuits 50(7): 1592-1603 (2015) - [c10]Md Shakil Akter, Rohan Sehgal
A 66 dB SNDR pipelined split-ADC using class-AB residue amplifier with analog gain correction. ESSCIRC 2015: 315-318 - [c9]Jan Mulder, Davide Vecchi, Yi Ke, Stefano Bozzola, Mark Core, Nitz Saputra, Qiongna Zhang, Jeff Riley, Han Yan, Mattia Introini, Sijia Wang, Christopher M. Ward, Jan R. Westra, Jiansong Wan, Klaas Bult:
26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. ISSCC 2015: 1-3 - 2014
- [j10]Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Zeng Zeng, Jan Mulder, Sijia Wang, Klaas Bult:
A 1.5 mW 68 dB SNDR 80 Ms/s 2 × Interleaved Pipelined SAR ADC in 28 nm CMOS. IEEE J. Solid State Circuits 49(12): 2835-2845 (2014) - [c8]Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. CICC 2014: 1-8 - [c7]Rohan Sehgal
A 12b 53 mW 195 MS/s pipeline ADC with 82dB SFDR using split-ADC calibration. ESSCIRC 2014: 67-70 - [c6]Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. ISSCC 2014: 146-147 - [c5]Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult:
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. ISSCC 2014: 200-201 - 2013
- [j9]Silvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen, Davide Guermandi, Xiaodong Liu, Erol Arslan, Frank M. L. van der Goes, Klaas Bult:
A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3 < -58 dBc in 40 nm CMOS. IEEE J. Solid State Circuits 48(7): 1595-1604 (2013) - 2011
- [j8]Davide Vecchi, Jan Mulder, Frank M. L. van der Goes, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800 MS/s Dual-Residue Pipeline ADC in 40 nm CMOS. IEEE J. Solid State Circuits 46(12): 2834-2844 (2011) - [c4]Jan Mulder, Frank M. L. van der Goes, Davide Vecchi, Jan R. Westra, Emre Ayranci, Christopher M. Ward, Jiansong Wan, Klaas Bult:
An 800MS/s dual-residue pipeline ADC in 40nm CMOS. ISSCC 2011: 184-186
2000 – 2009
- 2009
- [j7]Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12 bit 2.9 GS/s DAC With IM3 ≪ -60 dBc Beyond 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits 44(12): 3285-3293 (2009) - [c3]Klaas Bult:
Embedded analog-to-digital converters. ESSCIRC 2009: 52-64 - [c2]Chi-Hung Lin, Frank M. L. van der Goes, Jan R. Westra, Jan Mulder, Yu Lin, Erol Arslan, Emre Ayranci, Xiaodong Liu, Klaas Bult:
A 12b 2.9GS/s DAC with IM3 ≪-60dBc beyond 1GHz in 65nm CMOS. ISSCC 2009: 74-75 - 2004
- [j6]Jan Mulder, Christopher M. Ward, Chi-Hung Lin, David Kruse, Jan R. Westra, Marcel Lugthart, Erol Arslan, Rudy J. van de Plassche, Klaas Bult, Frank M. L. van der Goes:
A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. IEEE J. Solid State Circuits 39(12): 2116-2125 (2004)
1990 – 1999
- 1999
- [j5]Alan Y. Kwentus, Patrick Pai, Steven Jaffe, Ray Gomez, Shauhyuarn Sean Tsai, Tom Kwan, Hing T. Hung, Young J. Shin, Vin Hue, Darwin Cheung, Raheel A. Khan, Christopher M. Ward, Mong-Kai Ku, Kenneth Choi, Jim Searle, Klaas Bult, Kelly B. Cameron, Jason Demas, Charles Reames, Henry Samueli:
A single-chip universal digital satellite receiver with 480-MHz IF input. IEEE J. Solid State Circuits 34(11): 1634-1646 (1999) - 1998
- [j4]Chi-Hung Lin, Klaas Bult:
A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2. IEEE J. Solid State Circuits 33(12): 1948-1958 (1998) - [c1]Mehdi Hatamian, Oscar E. Agazzi, John Creigh, Henry Samueli, Andrew J. Castellano, David Kruse, Avi Madisetti, Nariman Yousefi, Klaas Bult, Patrick Pai, Myles Wakayama, Mike M. McConnell, Marty Colombatt:
Design considerations for gigabit Ethernet 1000Base-T twisted pair transceivers. CICC 1998: 335-342 - 1997
- [j3]Klaas Bult, Aaron Buchwald:
An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2. IEEE J. Solid State Circuits 32(11): 1887-1895 (1997)
1980 – 1989
- 1989
- [j2]Hans Wallinga, Klaas Bult:
Design and analysis of CMOS analog signal processing circuits by means of a graphical MOST model. IEEE J. Solid State Circuits 24(3): 672-680 (1989) - 1988
- [j1]Klaas Bult, Hans Wallinga:
A CMOS analog continuous-time delay line with adaptive delay-time control. IEEE J. Solid State Circuits 23(3): 759-766 (1988)
Coauthor Index
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