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IEEE Design & Test of Computers, Volume 5
Volume 5, Number 1, February 1988
- J. R. Armstrong:
Chip-level modeling with HDLs. 8-18 - Chad L. Mitchell, Michael J. Flynn:
A workbench for computer architects. 19-29 - Sumit Ghosh:
Using Ada as an HDL. 30-42 - Joshua S. L. Wong, David W. Y. Kwok:
A single-row transformation technique. 43-47
Volume 5, Number 2, April 1988
- Vishwani D. Agrawal, Kwang-Ting Cheng, Daniel D. Johnson, Tonysheng Lin:
Designing circuits with partial scan. 8-15 - Ed O. Schlotzhauer:
Real-world board test effectiveness. 16-23 - Algirdas J. Gruodis, Dale E. Hoffman:
250-MHz advanced test systems. 24-35 - Duane S. Boning, Dimitri A. Antoniadis:
A workstation approach to IC process and device design. 36-47
Volume 5, Number 3, June 1988
- Peter M. Maurer:
Design verification of the WE 32106 math accelerator unit. 11-21 - Charles E. Stroud, Ronald R. Munoz, David A. Pierce:
Behavioral model synthesis with Cones. 22-30 - Sumit Ghosh:
Behavioral-level fault simulation. 31-42 - Tom E. Kirkland, M. Ray Mercer:
Algorithms for automatic test pattern generation. 43-55 - Robert J. Powers:
Throughput advantages of asynchronous prober control. 56-63
Volume 5, Number 4, August 1988
- Xi-an Zhu, Melvin A. Breuer:
Analysis of testable PLA designs. 14-28 - Paul H. Bardell, William H. McAnney:
Built-in test for RAMs. 29-36 - Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier:
Built-in self-test of a CMOS ALU. 38-48
Volume 5, Number 5, October 1988
- Kenneth D. Wagner:
Clock system design. 9-27 - Atsushi Kara, Ravi Rastogi, Kazuhiko Kawamura:
An expert system to automate timing design. 28-40 - Xi-an Zhu, Melvin A. Breuer:
A knowledge-based system for selecting test methodologies. 41-59 - Hideo Fujiwara, Yuzo Takamatsu, Takashi Nanya, Teruhiko Yamada, Hideo Tamamoto, Kiyoshi Furuya:
Test research in Japan. 60-79
Volume 5, Number 6, December 1988
- Ronald A. Rohrer:
Evolution of the electronic design automation industry. 8-13 - Tsuneta Sudo:
Design automation systems in Japan. 14-21 - Charles E. Stroud:
Automated BIST for sequential logic synthesis. 22-32 - Derek L. Beatty, Randal E. Bryant:
Incremental switch-level analysis. 33-42 - Ren-Song Tsay, Ernest S. Kuh, Chi-Ping Hsu:
PROUD: a sea-of-gates placement algorithm. 44-56 - Leendert M. Huisman:
The reliability of approximate testability measures. 57-67
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