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VLSI-SoC 2010: Madrid, Spain
- 18th IEEE/IFIP VLSI-SoC 2010, IEEE/IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Madrid, Spain, 27-29 September 2010. IEEE 2010
Keynote
- Jayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt
, Jeffrey L. Krichmar
Towards reverse engineering the brain: Modeling abstractions and simulation frameworks. 1-6
Systems-On-Chip and Networks-on-Chip Design
- Eliyah Kilada, Shomit Das, Kenneth S. Stevens:
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study. 7-12 - Mojtaba Valinataj
A fault-aware, reconfigurable and adaptive routing algorithm for NoC applications. 13-18 - Wen-Chung Tsai, Kuo-Chih Chu, Sao-Jie Chen
TM-FAR: Turn-Model based Fully Adaptive Routing for Networks on Chip. 19-24 - Andy Motten, Luc Claesen:
A binary adaptable window SoC architecture for a stereo vision based depth field processor. 25-30 - Debora Matos, Miklecio Costa, Luigi Carro
Network interface to synchronize multiple packets on NoC-based Systems-on-Chip. 31-36 - Amit Berman
Order is power: Selective Packet Interleaving for energy efficient Networks-on-Chip. 37-42
Prototyping, Verification and Modeling
- Paolo Meloni
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. 43-48 - Rawan Abdel-Khalek, Valeria Bertacco:
SoCGuard: A runtime verification solution for the functional correctness of SoCs. 49-54 - Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan:
Enhancing post-silicon processor debug with Incremental Cache state Dumping. 55-60 - Nicola Bombieri
Model checking on TLM-2.0 IPs through automatic TLM-to-RTL synthesis. 61-66
Poster Session 1
- Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Power-aware FPGA routing fabrics and design tools. 67-72 - Zohreh Karimi, Majid Sarrafzadeh:
Fine-grained post placement voltage assignment considering level shifter overhead. 73-78 - Niccolò Battezzati, Luca Sterpone
A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs. 79-84 - Delasa Aghamirzaie, Seyyed Ahmad Razavi, Morteza Saheb Zamani
Reduction of process variation effect on FPGAs using multiple configurations. 85-90 - Pramod Kumar Meher:
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks. 91-95 - Sergey Sofer, Valery Neiman, Eyal Melamed-Cohen:
Synchronous duty cycle correction circuit. 96-100 - Ding-Guo Lin, Bing-Hsun Lu, Herming Chiueh:
An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector. 101-104 - François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, Michel Robert:
Spatial EM jamming: A countermeasure against EM Analysis? 105-110 - Yngvar Berg:
Ultra low voltage and high speed CMOS flip-flop using floating-gates. 111-114 - Yngvar Berg:
Static ultra-low-voltage high-speed CMOS logic and latches. 115-118 - Héctor Pettenghi
An improved RNS generator 2n +/- k based on threshold logic. 119-124 - Jongpil Jung, Seonpil Kim, Chong-Min Kyung:
Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems. 125-130 - Wei-Che Tseng, Chun Jason Xue
Optimal scheduling to minimize non-volatile memory access time with hardware cache. 131-136 - Christos Ttofis, Agathoklis Papadopoulos, Theocharis Theocharides
A reconfigurable MPSoC-based QAM modulation architecture. 137-142 - Khawla Hamwi, Omar Hammami:
Design and implementation of MPSoC single chip with butterfly network. 143-148 - Fengda Sun, Alessandro Cevrero, Panagiotis Athanasopoulos, Yusuf Leblebici:
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs. 149-154 - Christos Baloukas, Lazaros Papadopoulos, Robert Pyka, Dimitrios Soudris
An automatic framework for dynamic data structures optimization in C. 155-160
Analog and Mixed Signal IC Design
- Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni:
Adaptive logical control of RF LNA performances for efficient energy consumption. 161-166 - Hui Shao, Chi-Ying Tsui
A single inductor DIDO DC-DC converter for solar energy harvesting applications using band-band control. 167-172 - Oussama Elissati, Eslam Yahya, Sébastien Rieubon, Laurent Fesquet:
A high-speed high-resolution low-phase noise oscillator using self-timed rings. 173-178 - Jing Guo, Bing Liu, George Jie Yuan:
A highly linear wide dynamic range detector for cell recording with microelectrode arrays. 179-182
Digital Signal Processing and Image Processing IC Design
- Christian Benkeser, Andreas Bubenhofer, Qiuting Huang:
A 1mm2 1.3mW GSM/EDGE digital baseband receiver ASIC in 0.13 µm CMOS. 183-188 - Markus Wenk, Lukas Bruderer, Andreas Burg
Area- and throughput-optimized VLSI architecture of sphere decoding. 189-194 - Gabriel Caffarena
Fast fixed-point optimization of DSP algorithms. 195-200 - Pramod Kumar Meher:
Novel input coding technique for high-precision LUT-based multiplication for DSP applications. 201-206 - Abdulkadir Akin, Mert Cetin, Burak Erbagci, Ozgur Karakaya, Ilker Hamzaoglu:
An adaptive bilateral motion estimation algorithm and its hardware architecture. 207-212
Digital System Design and Architectures
- Kuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin:
A decimal squarer with efficient partial product generation. 213-218 - Somsubhra Talapatra, Hafizur Rahaman
Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm). 219-224 - Yngvar Berg:
Novel ultra low-voltage and high speed domino CMOS logic. 225-228 - Roman Plyaskin, Alejandro Masrur, Martin Geier
High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations. 229-234 - Bruno Zatt, Cláudio Machado Diniz, Luciano Volcan Agostini
Timing and interface communication analysis of H.264/AVC encoder using SystemC model. 235-240
Circuits and Systems for New Applications
- Oscar Alonso
Control electronics integration toward endoscopic capsule robot performing legged locomotion and illumination. 241-246 - Luc Claesen, Peter Vandoren, Tom Van Laerhoven, Andy Motten, Domien Nowicki, Tom De Weyer, Frank Van Reeth, Eddy Flerackers:
Smart camera SoC system for interactive real-time real-brush based digital painting systems. 247-252 - Joachim Neves Rodrigues, Omer Can Akgun
A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS. 253-258 - Mohamed Abdelsalam, M. Wahba, M. Abdelmoneum, David Duarte, Yehia Ismail:
Supporting circuitry for a fully integrated micro electro mechanical (MEMS) oscillator in 45 nm CMOS technology. 259-263 - Michele Magno
Energy aware multimodal embedded video surveillance. 264-269
Green Computing
- Roberto Gioiosa:
Towards sustainable exascale computing. 270-275 - Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla
Trends and techniques for energy efficient architectures. 276-279
Logic Synthesis, Testability and Design for Test
- Anna Bernasconi
Logic synthesis and testability of D-reducible functions. 280-285 - Jimson Mathew, Savita Banerjee, Hafizur Rahaman
On the synthesis of attack tolerant cryptographic hardware. 286-291 - Diego Jaccottet, Eduardo Costa
Design of low-complexity and high-speed digital Finite Impulse Response filters. 292-297 - Mariza Botelho, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Érika F. Cota, Luigi Carro:
A broad strategy to detect crosstalk faults in network-on-chip interconnects. 298-303
Architectures for DSP and Video Processing Applications
- Maher Jridi
A low-power, high-speed DCT architecture for image compression: Principle and implementation. 304-309 - João S. Altermann, Eduardo A. C. da Costa
Fast forward and inverse transforms for the H.264/AVC standard using hierarchical adder compressors. 310-315 - Ronaldo Husemann, Mariano Majolo, Victor Guimarães, Altamiro Amadeu Susin, Valter Roesler, José Valdeni de Lima:
Hardware integrated quantization solution for improvement of computational H.264 encoder module. 316-321 - Gabriel Caffarena
Architectural synthesis of DSP circuits under simultaneous error and time constraints. 322-327
Deep Submicron Design
- Milos Stanisavljevic, Alexandre Schmid
Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation. 328-334 - Marc Pons
VCTA: A Via-Configurable Transistor Array regular fabric. 335-340
Manycore Architectures
- Nicolas Ventroux, Tanguy Sassolas, Raphaël David, Guillaume Blanc, Alexandre Guerre, Charly Bechara:
SESAM extension for fast MPSoC architectural exploration and dynamic streaming applications. 341-346
Low Power Circuit Design
- Hailong Jiao, Volkan Kursun
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. 347-351 - Seunghan Lee, Kyungsu Kang, Chong-Min Kyung:
Temperature- and bus traffic- aware data placement in 3D-stacked cache. 352-357 - Alberto Bonanno, Alberto Bocca, Alberto Macii
Power-aware partitioning of data converters. 358-363 - Nazrul Anuar
4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR. 364-368
Physical Design for 3D Integration and Communication Systems
- Tsung-Yi Ho
Fast legalization for standard cell placement with simultaneous wirelength and displacement minimization. 369-374 - Roberto Cardu, Eleonora Franchi, Roberto Guerrieri, Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo:
Characterization of chip-to-chip wireless interconnections based on capacitive coupling. 375-380 - Aaron V. T. Do, Chirn Chye Boon
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. 381-386 - Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. 387-391 - Kuo-Che Hong, Herming Chiueh:
A 36-mW continuous-time sigma-delta modulator with 74db dynamic range and 10-MHz bandwidth. 392-395
New Architectures for Reconfigurable Systems-on-chip and Multiprocessor Systems-on-chip
- Chengmo Yang, Alex Orailoglu:
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations. 396-401 - Ji Kong, Peilin Liu:
A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC. 402-407 - Bruno Francisco, Frederico Pratas, Leonel Sousa
Unifying stream based and reconfigurable computing to design application accelerators. 408-413 - Alessandro Panella, Marco D. Santambrogio
A design workflow for dynamically reconfigurable multi-FPGA systems. 414-419 - Chengmo Yang, Chun Jason Xue
Fine-grained adaptive CMP cache sharing through access history exploitation. 420-425
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