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SoCC 2014: Las Vegas, NV, USA
- Kaijian Shi, Thomas Büchner, Danella Zhao, Ramalingam Sridhar:
27th IEEE International System-on-Chip Conference, SOCC 2014, Las Vegas, NV, USA, September 2-5, 2014. IEEE 2014, ISBN 978-1-4799-3378-5 - Kaijian Shi:
Message from conference general chair. iv-v - Thomas Büchner, Danella Zhao:
Message from program chairs. vi-vii - Mohammad Tehranipoor, Charles Knapp:
T1A: Opportunities and challenges for secure hardware and verifying trust in integrated circuits. xxxiii-xxxiv - Gerard M. Blair:
T2A: Clock implementation: A question of timing. xxxv-xxxvi - Partha Pratim Pande, Alireza Nojeh
, André Ivanov:
T1B: Wireless NoC as interconnection backbone for multicore chips: Promises and challenges. xxxvii-xxxviii - Alireza Nojeh
T2B: Carbon nanotubes and opportunities for wireless on-chip interconnect. xxxix-xli - Ümit Y. Ogras:
T3A: Design and managements of multiprocessor systems-on-chips. xlii - Andrew Marshall:
T4A: System-on-chip design using Tri-gate technology. xliii - Han Sun:
T3B: Recent advancements in fiber optic transmission enabled by highly integrated mixed signal SoC and advanced digital signal processing. xliv - Wolfgang Kunz, Dominik Stoffel, Joakim Urdahl:
T4B: Formal verification in system-on-chip design: Scientific foundations and practical methodology. xlv-xlvi - Tom Beckley:
Keynote speaker: "The Internet of Every-Thing: EDA perspectives". 2 - Scott Runner:
Plenary speaker: "SoCs for Mobile Applications: Systems from 0 MPH to over 100 MPH". 3 - Ashok Jaiswal, Dominik walk, Yuan Fang, Klaus Hofmann:
Low-power high-speed on-chip asynchronous Wave-pipelined CML SerDes. 5-10 - Peter Gadfort
A power efficient reconfigurable system-in-stack: 3D integration of accelerators, FPGAs, and DRAM. 11-16 - Tatsuya Kamakari, Shinichi Nishizawa, Tohru Ishihara
Variation-aware Flip-Flop energy optimization for ultra low voltage operation. 17-22 - Nahid M. Hossain, Md Belayat Hossain, Masud H. Chowdhury:
Multilayer layer graphene nanoribbon flash memory: Analysis of programming and erasing operation. 24-28 - Oliver Arnold, Benedikt Noethen, Gerhard P. Fettweis:
CM_ISA++: An instruction set for dynamic task scheduling units for more than 1000 cores. 29-34 - Sheheeda Manakkadu, Sourav Dutta
Power aware parallel computing on asymmetric multiprocessor. 35-40 - Shinichi Nishizawa, Tohru Ishihara
Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation. 42-47 - Santhosh Kumar Rethinagiri, Oscar Palomar
DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level. 48-53 - Weiwei Shi, Oliver Chiu-sing Choy:
A novel ratioed logic style for faster subthreshold digital circuits based on 90 nm CMOS and below. 54-57 - Hongjiang Song, Zhijian Lu, Tao Luo, Jennifer Blain Christen
A CMOS self-powered monolithic light direction sensor with SAR ADC. 58-62 - Vinod Pangracious
On wiring delays reduction of tree-based FPGA using 3-D fabric. 64-69 - Poona Bahrebar, Azarakhsh Jalalvand, Dirk Stroobandt:
Adaptive multicast routing method for 3D mesh-based Networks-on-Chip. 70-75 - Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang
Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. 76-81 - Jongyoon Hwang, Dongjoo Kim, Mun-Kyo Lee, Sun-Phil Nah, Minkyu Song:
Design of a 9-bit 1GS/s CMOS folding A/D converter with a boundary error reduction technique. 83-87 - Gi-Yoon Lee, Kwang Sub Yoon:
Design of a low power CMOS 10bit flash-SAR ADC. 88-91 - Siavash Moghadami, Farzaneh Jalaibidgoli, Shahab Ardalan:
A systematic methodology to design high power terahertz and submillimeter-wave amplifiers. 92-97 - Chorng-Sii Hwang, Ting-Li Chu, Wen-Cheng Chen:
A clock generator based on multiplying delay-locked loop. 98-102 - M. Wagih Ismail, Hassan Mostafa
A new design methodology for Voltage-to-Time Converters (VTCs) circuits suitable for Time-based Analog-to-Digital Converters (T-ADC). 103-108 - Ahmed Ginawi, Tian Xia, Robert Gauthier:
Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event. 109-114 - Shreeyash Salunke, Shreyas Darne, Keval Shah, Rishikesh Dhamapurkar:
Electromyograph data acquisition and application using Cypress Programmable System on Chip. 115-118 - Vijay K. Jain:
Microcells for ICA-SOC for remote sensing of high energy radiation. 119-124 - Jun-Hua Chiang, Bin-Da Liu, Shih-Ming Chen, Hong-Tzer Yang
A low supply voltage mixed-signal maximum power point tracking controller for photovoltaic power system. 125-129 - Tao Li, Greg Sadowski:
Design and implementation of novel source synchronous interconnection in modern GPU chips. 130-135 - Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang:
PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. 136-139 - Ramesh Nair, Ranga Vemuri
MITH-Dyn: A multi Vth dynamic logic design style using mixed mode FinFETs. 140-145 - David Kadjo, Ümit Y. Ogras
Towards platform level power management in mobile systems. 146-151 - Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Analysis of the current-voltage characteristics of Silicon on Ferroelectric Insulator Field Effect Transistor (SOF-FET). 152-155 - Azzedin D. Es-Sakhi, Masud H. Chowdhury:
Multichannel Tunneling Carbon Nanotube Field Effect Transistor (MT-CNTFET). 156-159 - Chi-Hao Hong, Yi-Wei Chiu, Jun-Kai Zhao, Shyh-Jye Jou, Wen-Tai Wang, Reed Lee:
A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology. 160-164 - Ali Mahdoum:
Networks on chip design for real-time systems. 165-170 - Farzad Radfar, Masoud Zabihi
Comparison between optimal interconnection network in different 2D and 3D NoC structures. 171-176 - Ahmed Aldammas, Adel Soudani, Abdullah Al-Dhelaan:
Flow control solution for efficient communication and congestion avoidance in NoC. 177-182 - Divya Pathak, Ioannis Savidis:
Run-time voltage detection circuit for 3-D IC power delivery. 183-187 - He Zhou, Linda S. Powers, Janet Roveda:
Collision array based workload assignment for Network-on-Chip concurrency. 188-191 - Yikun Jiang, Mei Yang:
On circuit design of on-chip non-blocking interconnection networks. 192-197 - Boris Traskov, Ulrich Langenbach, Klaus Hofmann, Peter Gregorius:
Hardware architecture of an Internet Protocol Version 6 processor. 198-203 - Abdulfattah Mohammad Obeid, Syed Manzoor Qasim
Flexible reconfigurable architecture for DSP applications. 204-209 - Nicolas Serna, François Verdier:
Very fast co-simulation model and accurate on-the-fly performance estimation methodology for heterogeneous MPSoC. 210-215 - J. Thomas Pawlowski:
Keynote speaker. 217-218 - Jeffrey D. Brown:
Plenary speaker. 219 - Ching-Che Chung
An all-digital on-chip abnormal temperature warning sensor for dynamic thermal management. 221-224 - Muhammad Tanveer, Johan Borg
Time stretcher for a time-to-digital converter with a precisely matched current mirror. 225-230 - Fang-Ting Chou, Zong-Yi Chen, Chung-Chih Hung:
A 10-bit 250MS/s low-glitch binary-weighted digital-to-analog converter. 231-235 - Haibo Wang, Ram Harshvardhan Radhakrishnan:
An accelerated successive approximation technique for analog to digital converter design. 236-241 - Hemanta Kumar Mondal
An energy efficient wireless Network-on-Chip using power-gated transceivers. 243-248 - Ankit Shah, Naseef Mansoor, Ben Johnstone, Amlan Ganguly, Sonia Lopez Alarcon:
Heterogeneous photonic Network-on-Chip with dynamic bandwidth allocation. 249-254 - Cristinel Ababei, Nicholas Mastronarde:
Benefits and costs of prediction based DVFS for NoCs at router level. 255-260 - Nickvash Kani, Azad Naeemi
Wiring resource minimization for physically-complex Network-on-Chip architectures. 261-266 - Shahid Ikram, David Asher, Isam Akkawi, Jack Perveiler, Jim Ellis:
A framework for specifying, modeling, implementation and verification of SOC protocols. 268-273 - Satish Grandhi, Christian Spagnol, Jiaoyan Chen, Emanuel M. Popovici, Sorin Cotafona:
Reliability aware logic synthesis through rewriting. 274-279 - Moeen Hassanalieragh, Tolga Soyata
Solar-supercapacitor harvesting system design for energy-aware applications. 280-285 - Jyu-Yuan Lai, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou, Tung-Hua Yeh, Liang-Chia Cheng, Juin-Ming Lu:
Methodology of exploring ESL/RTL many-core platforms for developing embedded parallel applications. 286-291 - Matt Briggs, Payman Zarkesh-Ha:
Evaluating mobile SOCs as an energy efficient DSP platform. 293-298 - Chen Yang, Yizhuang Xie, He Chen, Yi Deng:
New quantization error assessment methodology for fixed-point pipeline FFT processor design. 299-305 - Bharat Garg, Nitesh K. Bharadwaj, G. K. Sharma:
Energy scalable approximate DCT architecture trading quality via boundary error-resiliency. 306-311 - Bastian Mohr, Ye Zhang, Jan Henning Mueller, Stefan Heinen:
Compensating imperfections in RF-DAC based transmitters using LUT-based predistortion. 312-316 - Hiroyuki Yamauchi
Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs. 318-323 - Unni Chandran, Dan Zhao:
Cost-optimal design of wireless pre-bonding test framework. 324-329 - Cédric Marchand
IP watermark verification based on power consumption analysis. 330-335 - Vasant Easwaran, Virendra Bansal, Greg Shurtz, Rahul Gulati, Mihir N. Mody, Prashant Karandikar, Prithvi Shankar:
A unique non-intrusive approach to non-ATE Based cul-de-sac SoC debug. 336-339 - Vikram B. Suresh, Wayne P. Burleson:
REFLEX: Reconfigurable logic for entropy extraction. 341-346 - Abhilash K. N, M. B. Srinivas:
A reconfigurable 0-L1-L2 S-MASH2 modulator with high-level sizing and power estimation. 347-352 - Keissy Guerra Perez, Xin Yang, Sandra Scott-Hayward, Sakir Sezer:
A configurable packet classification architecture for Software-Defined Networking. 353-358 - Cory E. Merkel, Dhireesha Kudithipudi:
A stochastic learning algorithm for neuromemristive systems. 359-364 - Paul Eremenko:
Banquet speaker. 369 - Dhireesha Kudithipudi, Cory E. Merkel, Yu Kee Ooi, Qutaiba Saleh
On designing circuit primitives for cortical processors with memristive hardware. 371-376 - Hai Li
Emerging memristor technology enabled next generation cortical processor. 377-382 - Tarek M. Taha, Raqibul Hasan, Chris Yakopcic:
Memristor crossbar based multicore neuromorphic processors. 383-389 - Raj S. Dua, Siddharth Katare, Narayanan Natarajan:
Resistorless on-die high voltage power supply noise measurement. 390-392 - Ye Zhang, Jan Henning Mueller, Muh-Dey Wei, Ralf Wunderlich, Stefan Heinen:
Design of a low power multistandard transceiver chain based on current-reuse VCO. 393-396 - Bill Jason Tomas, Yingtao Jiang, Mei Yang:
SoC Scan-Chain verification utilizing FPGA-based emulation platform and SCE-MI interface. 398-403 - Sridhar Srinivasan, Ellis Cohen, Mark Hofmann:
A new approach using symbolic analysis to compute path-dependent effective properties preserving hierarchy. 404-408 - Mohammad M. Uzzal, Payman Zarkesh-Ha, Jeremy S. Edwards, Ezequiel Coelho, Priyanka Rawat:
A highly sensitive ISFET using pH-to-current conversion for real-time DNA sequencing. 410-414 - Hongjiang Song, Chen Chen, Meng-Wei Lin, Kaijun Li, Jennifer Blain Christen
A neural rehabilitation chip with neural recording, peak detection, spike rate counter, and biphasic neural stimulator. 415-419 - Guo-Zua Wu, Song-Nien Tang, Chih-Chi Chang, Chien-Ju Lee, Kuan-Hsien Lin, Oscal T.-C. Chen:
High-frequency and power-efficiency ultrasound beam-forming processor for handheld applications. 420-424 - Jan Henning Mueller, Ye Zhang, Lei Liao, Aytac Atac, Zhimiao Chen, Bastian Mohr, Stefan Heinen:
A low complexity multi standard dual band CMOS polar transmitter for smart utility networks. 426-430 - Sushrant Monga, Shouri Chatterjee
A 25.5mW 10Gb/s inductorless receiver with an adaptive front-end in 0.13 µm CMOS. 431-436 - Xin Yang, Sakir Sezer, Shane O'Neill:
A hardware acceleration scheme for memory-efficient flow processing. 437-442 - Tahseen Shakir, Manoj Sachdev:
A body-bias based current sense amplifier for high-speed low-power embedded SRAMs. 444-448 - Hooman Farkhani, Ali Peiravi
Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective. 449-454 - Chao-Kuei Chung, Chien-Yu Lu, Zhi-Hao Chang, Shyh-Jye Jou, Ching-Te Chuang, Ming-Hsien Tu, Yu-Hsian Chen, Yong-Jyun Hu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao:
A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. 455-462
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