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ITC 1989: Washington, D.C., USA
- Proceedings International Test Conference 1989, Washington, D.C., USA, August 1989. IEEE Computer Society 1989
Session 2: Sequential ATPG
- Xaiolin Wang, Fredrick J. Hill, Zhengkin Mi:
A Sequential Circuit Fault Simulation by Surrogate Fault Propagation. 9-18 - Sybille Hellebrand, Hans-Joachim Wunderlich:
The Pseudo-Exhaustive Test of Sequential Circuits. 19-27 - Michael H. Schulz, Elisabeth Auth:
Essential: An Efficient Self-Learning Test Pattern Generation Algorithm for Sequential Circuits. 28-37 - Rahul Razdan, M. Anwaruddin, Predrag G. Kovijanic, R. Ganesh, H.-C. Shih:
An Interactive Sequential Test Pattern Generation System. 38-46
Session 3: Boundary Scan Algorithms and Implementation
- Sue Vining:
Tradeoff Decisions Made for P11149.1 Controller Design. 47-54 - Anton T. Dahbura, M. Ümit Uyar, Chi W. Yau:
An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller. 55-62 - Najmi T. Jarwala, Chi W. Yau:
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. 63-70 - Najmi T. Jarwala, Chi W. Yau:
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. 71-77
Session 4: Systems Test I
- Moshe Ben-Bassat, Defna Ben-Arie, Israel Beniaminy, Jonathan Cheifetz, Michael Klinger:
A Proposed Benchmark Unit for Evaluating Electronic Troubleshooting Expert Systems. 78-86 - David K. Oka:
Transmission Line Simulation for Testing ISDN Devices. 87-93 - Carol Pyron, Rex Sallade:
CAE Functionality for Verification of Diagnostic Programs. 94-102 - Miroslaw Malek, Antoine N. Mourad, Mihir Pandya:
Topological Testing. 103-110
Session 5: Mixed Signal Testing I
- Solomon Max:
Fast Accurate and Complete ADC Testing. 111-117 - Alice McKeon, Antony Wakeling:
Fault Diagnosis in Analogue Circuits Using AI Techniques. 118-123 - Kohei Akiyama, Hiroshi Nishimura, Kyoji Anazawa, Akito Kishida, Nobuyuki Kasuga:
High-Resolution Analog Measurement on Mixed-Signal LSI Tester. 124-128 - Kenneth R. Chin:
Functional Testing of Circuits and SMD Boards with Limited Nodal Access. 129-143
Session 6: Delay Test Generation
- Srinivas Devadas:
Delay Test Generation for Synchronous Sequential Circuits. 144-152 - Jacques Benkoski, Andrzej J. Strojwas:
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. 153-160 - Kazumi Hatayama, Mitsuji Ikeda, Terumine Hayashi, Masahiro Takakura, Kuniaki Kishida, Shun Ishiyama:
Enhanced Delay Test Generator for High-Speed Logic LSIs. 161-165
Session 7: Boundary Scan in Board and Prototype Testing Today
- Peter Hansen:
Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices as Virtual ATE Channels. 166-173 - Andy Halliday, Greg Young, Alfred L. Crouch:
Prototype Testing Simplified by Scannable Buffers and Latches. 174-181 - W. David Ballew, Lauren M. Streb:
Board-Level Boundary-Scan: Regaining Observability with an Additional IC. 182-189
Session 8: Coupling, Distribution and Probes
- J. R. Birchak, H. K. Haill:
Coupling Coefficients for Signal Lines Separated by Ground Lines on PC Boards. 190-198 - Ching-Wen Hsue:
Clock Signal Distribution Network for High-Speed Testers. 199-207 - Norman Nadeau, Sylvie Perreault:
An Analysis of Tungsten Probes' Effect on Yield in a Production Wafer Probe Environment. 208-215
Session 9: Mixed Signal Testing II
- John L. LaMay, Dan C. Caldwell:
A Telecommunications Line Interface Test System Architecture. 216-221 - Kenneth Lanier:
Methods of Test Waveform Synthesis for High-Speed Data Communication Devices. 222-230 - Thomas H. Morrin:
Mixed-Mode Simulation for Time-Domain Fault Analysis. 231-241
Session 10: Panel Session, Design and Test in the University
- Richard Absher, J. E. (Ned) Lecky:
Engineering Curricula for "Meeting the Tests of Time". 242-244 - Sami A. Al-Arian:
Design and Test in the Universities. 245-245 - Donald W. Bouldin:
The Push for Test in Universities. 246-246 - Kenneth Rose:
Design Assurance in a University Setting. 247-248
Session 11: Panel Session, SPC/TQM What It Is ... What It Is Not
- Melisa N. Vittrup, Glendon S. Frashure:
A Fundamental Approach to SPC Implementation. 249-251
Session 13: Pattern Generation for Built-In-Self-Test
- Paul H. Bardell:
Calculating the Effects of Linear Dependencies in m-Sequences Used as Test Stimuli. 252-256 - Sheldon B. Akers, Winston Jansz:
Test Set Embedding in a Built-In Self-Test Environment. 257-263 - Franc Brglez, Gershon Kedem, Clay Gloster:
Hardware-Based Weighted Random Pattern Generation for Boundary Scan. 264-274
Session 14: Systems Test II
- David L. Landis:
A Self-Test System Architecture for Reconfigurable WSI. 275-282 - Yoichi Tsubuku, Takao Nishida, Hiroshi Shiga, Ken Ohga, Hirohisa Nishine, Mamoru Kaneko:
Main Frame Diagnosis Support System. 283-289 - Robert F. Lusch, Endre F. Sarkany:
Techniques for Improved Testability in the IBM ES/9370 System. 290-294
Session 15: Practical Quality Isues- Today
- James Westover:
Practical Test Strategies for Users of 100 PPM ICs. 295-303 - Ron Santella:
The Role of Test in a "Continuous Improvement" Environment. 304-308 - Kenneth R. Stuchlik:
IC Characteristic Matching for Optimal System Performance. 309-315
Session 16: Design for Test of VLSI Memories
- Rainer Kraus, Oskar Kowarik, Kurt Hoffmann, Dieter Oberle:
Design for Test of Mbit DRAMs. 316-321 - Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi, Kazuyasu Fujishima:
A New Array Architecture for Parallel Testing in VLSI Memories. 322-326 - Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita:
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. 327-336
Session 17: Topics in Signature Analysis
- C. C. Chuang, Anup K. Gupta:
The Analysis of Parallel BIST by the Combined Markov Chain (CMC) Model. 337-343 - Dhiren Xavier, Robert C. Aitken, André Ivanov, Vinod K. Agarwal:
: Experiments on Aliasing in Signature Analysis Registers. 344-354 - Régis Leveugle, Gabriele Saucier:
Optimized Synthesis of Dedicated Controllers with Concurrent Checking Capabilities. 355-363
Session 18: Testability Analysis
- Raghu V. Hudli, Sharad C. Seth:
Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. 364-372 - C. H. Chen, Premachandran R. Menon:
An Approach to Functional Level Testability Analysis. 373-380 - Kurt H. Thearling, Jacob A. Abraham:
An Easily Computed Functional Level Testability Measure. 381-390
Session 19: Leading Edge Quality Issues
- Massimo Lanzoni, Piero Olivo, Bruno Riccò:
A Testing Technique to Characterize E^2PROM's Aging and Endurance. 391-396 - Eugene R. Hnatek, Billy R. Livesay:
Quality Issues of High Pin Count Fine Pitch VLSI Packages. 397-422 - Jerry M. Soden, R. Keith Treece, Michael R. Taylor, Charles F. Hawkins:
CMOS IC Stuck-Open Fault Electrical Effects and Design Considerations. 423-430
Session 20: Concepts in Memory Testing
- W. Malzfeldt, W. Mohr, H.-D. Oberle, K. Kodalle:
Fast Automatic Failbit Analysis for DRAMs. 431-438 - Jacob Savir, William H. McAnney, Salvatore R. Vecchio:
Testing for Coupled Cells in Random-Access Memories. 439-451 - Kenrick Koo, Steve Ramseyer, Al Tejeda:
A Testing Methodology for New-Generation Specialty Memory Devices. 452-460
Session 21: Hierarichical Test Generation
- P. N. Anirudhan, Premachandran R. Menon:
Symbolic Test Generation for Hierarchically Modeled Digital Systems. 461-469 - Thomas M. Sarfert, Remo G. Markgraf, Erwin Trischler, Michael H. Schulz:
Hierarchical Test Pattern Generation Based on High-Level Primitives. 470-479 - John D. Calhoun, Franc Brglez:
A Framework and Method for Hierarchical Test Generation. 480-490
Session 22: Synthesis for Testability
- Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton:
Redundancies and Don't Cares in Sequential Logic Synthesis. 491-500 - Daniel Brand, Vijay S. Iyengar:
Synthesis of Pseudo-Random Pattern Testable Designs. 501-508 - Sreejit Chakravarty:
A Testable Realization of CMOS Combinational Circuits. 509-518
Session 23: Process Improvement Aided by New Analytic Approaches
- David Grabel:
Data Verification: A Prerequisite for Heuristic Diagnostics. 519-526 - Wojciech Maly, Samir B. Naik:
Process Monitoring Oriented IC Testing. 527-532 - J. Patterson:
Improved System Design Through Proper Nesting of Test Levels. 533-542
Session 24: Logic ATE Architecture
- Gary J. Lesmeister:
The Linear Array Systolic Tester (LAST). 543-549 - Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater:
Low Cost Testing of High Density Logic Components. 550-557 - Shuji Kikuchi, Yoshihiko Hayashi, Takashi Matsumoto, Ryozou Yoshino, Ryuichi Takagi:
A 250 MHz Shared-Resource VLSI Test System with High Pin Count and Memory Test Capability. 558-566
Session 25: Panel Session, Random Vectors in External Testing: Free Lunch or Hidden Costs?
Session 26: Test Software
- Bruce A. Webster:
An Integrated Analog Test Simulation Environment. 567-571 - Wayne D. Dettloff, Melodie D. Tebbs:
The Omnitest System: A No-Generate, No-Compile, Interactive Test Methodology. 572-576 - Eric Paradis, David Stannard:
SASPL: A Test Program Productivity Analysis Tool. 577-584 - Eric Rosenfeld:
Issues for Mixed-Signal CAD-Tester Interface. 585-590
Session 27: Managing the Cost or VLSI Testing
- Michael W. Salter, Kemon P. Taschioglou:
Mainstream ATE: To Reduce LSI and VLSI Test Cost. 591-596 - Sheila O'Keefe:
Reconfigurable Resource Architecture Improves VLSI Tester Utilization. 597-604 - J. Stephen Pabst:
Cost Impacts of Automatic Test Equipment Purchase Decisions. 605-610
Session 28: Advanced Test Solutions In Today`s VLSI Processors
- William R. Mann:
R96MFX Test Strategy. 611-614 - Wallace Harwood, Mark McDermott:
Testability Features of the MC68332 Modular Microcontroller. 615-623 - Yasuyuki Nozuyama, Akira Nishimura, Jun Iwamura:
Implementation and Evaluation of Microinstruction-Controlled Self Test Using a Masked Microinstruction Scheme. 624-632
Session 29: Physical Defects ub VLSI Chips
- Marcel Jacomet:
FANTESTIC: Towards a Powerful Fault Analysis and Test Pattern Generator for Integrated Circuits. 633-642 - F. Camerik, P. A. J. Dirks, Jochen A. G. Jess:
Qualification and Quantification of Process-Induced Product-Related Defects. 643-652 - Scott F. Midkiff, Wern-Yan Koe:
Test Effectiveness Metrics and CMOS Faults. 653-659
Session 30: Design For Testability
- Frans P. M. Beenker, Rob Dekker, Rudi Stans, Max van der Star:
A Testability Strategy for Silicon Compilers. 660-669 - Yinan N. Shen, Fabrizio Lombardi:
Location and Identification for Single and Multiple Faults in Testable Redundant PLAs for Yield Enhancement. 670-678 - Chin-Long Wey:
Fault Location in Repairable Programmable Logic Arrays. 679-685
Session 31: Board Test I- Test Development and Applications
- Frank J. Langley, Ronald R. Boatright, Laurence Crosby:
Composite Electro-Optical Testing of Surface-Mount Device Boards-One Manufacturer's Experience. 686-691 - Michel Crastes de Paulet, Margot Karam, Gabriele Saucier:
Testability Expertise and Test Planning from High-Level Specifications. 692-699 - Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie:
Testing of Glue Logic Interconnects Using Boundary Scan Architecture. 700-711
Session 32: Advances in Fault Simulation
- Bill Underwood, Jack Ferguson:
The Parallel-Test-Detect Fault Simulation Algorithm. 712-717 - Srinivas Patil, Prithviraj Banerjee:
Fault Partitioning Issues in an Integrated Parallel Test Generation/Fault Simulation Environment. 718-726 - Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, Raffi Tutundjian:
Fault Simulation in a Pipelined Multiprocessor System. 727-734
Session 33: Practical Considerations in BIST Implementation
- Richard Illman, Stephen Clarke:
Built-In Self-Test of the Macrolan Chip. 735-744 - Yvon Savaria, Bruno Laguë, Bozena Kaminska:
A Pragmatic Approach to the Design of Self-Testing Circuits. 745-754 - Samuel H. Duncan:
A BIST Design Methodology Experiment. 755-762
Session 34: Board Test II- Architecture and Accuracy
- Jay M. Stepleton:
A New System Architecture for a Combined In-Circuit/Functional Tester. 763-772 - Barry A. Alcorn:
Writing Correct and Usable Specifications for Board Test: A Case Study. 773-786 - Phillip N. King:
Flexible, High-Performance Pin Electronics Implementation. 787-794
Session 35: New Topics in ATPG
- Tracy Larrabee:
Efficient Generation of Test Patterns Using Boolean Difference. 795-802 - Hyoung B. Min, William A. Rogers:
Search Strategy Switching: An Alternative to Increased Backtracking. 803-811 - Charles E. Stroud, Ahmed E. Barbour:
Design for Testability and Test Generation for Static Redundancy System Level Fault-Tolerant Circuits. 812-818
Session 36: CAE and Workstations
- Arif Samad, Martin Bell:
Automating ASIC Design-for-Testability: The VLSI Test Assistant. 819-828 - Arthur E. Downey:
"ATG" Test Generation Software. 829-837 - Jens Leenstra, Lambert Spaanenburg:
On the Design and Test of Asynchronous Macros Embedded in Synchronous Systems. 838-845
Session 37: Drivers, Detectors and Sensitivities.
- Christopher W. Branson:
A High Performance, 10-Volt Integrated Pin Electronics Driver. 846-853 - Stephen W. Bryson:
Custom Pin Electronics for VLSI Automatic Test Equipment. 854-859 - Steve Barton:
Characterization of High-Speed (Above 50 MHz) Devices Using Advance ATE-Techniques, Results and Device Problems. 860-868
Session 38: The Economics of Design-for-Testability
- Marc E. Levitt, Jacob A. Abraham:
The Economics of Scan Design. 869-874 - Chryssa Dislis, I. D. Dear, J. R. Miles, S. C. Lau, Anthony P. Ambler:
Cost Analysis of Test Method Environments. 875-883 - Bozena Kaminska, Yvon Savaria:
Design-for-Testability Using Test Design Yield and Decision Theory. 884-892
Session 39: ASIC Products-The Test Challenge
- Don Allingham, Pat Bashford, Mike Peters, Dean Vendl:
DesignTest^TM: A Solution to the Problems of ASIC Verification. 893-902 - George Swan, Yatin Trivedi, David J. Wharton:
CrossCheck: A Practical Solution for ASIC Testability. 903-908
Session 40: E-Beam Update
- Kazuhiro Sakashita, Takeshi Hashizume, Takashi Ohya, Isao Takimoto, Shuichi Kato:
Cell-Based Test Design Method. 909-916 - Yasuo Tokunaga, Jürgen Frosien:
High Performance Electron Beam Tester for Voltage Measurement on Unpassivated and Passivated Devices. 917-922 - Christopher G. Talbot, Suresh Rajan:
A Logic Analyzer Tool That Cuts E-Beam Prober Acquisition Times. 923 - D. J. Hall, Anthony W. Sloman, G. S. Plows:
Rapid Data Acquisition for E-Beam Testing. 928
Poster Session
- Michele Favalli, Piero Olivo, Maurizio Damiani, Bruno Riccò:
CMOS Design for Improved IC Testability. 934 - John C. Chan, Baxter F. Womack:
Diagnostics Based on Fault Signature. 935 - Piero Olivo, Maurizio Damiani, Bruno Riccò:
On the Design of Multiple-Input Shift-Registers for Signature Analysis Testing. 936 - Rolf Ernst, S. Sutarwala, J.-Y. Jou:
TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. 937 - David Haupert, Fu-Gin Chen, David Lee:
VLSI Package Reliability Risk Due to Accelerated Environmental Testing. 938
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