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ESSCIRC 2012: Bordeaux, France
- Proceedings of the 38th European Solid-State Circuit conference, ESSCIRC 2012, Bordeaux, France, September 17-21, 2012. IEEE 2012, ISBN 978-1-4673-2212-6
Joint ESSDERC/ESSCIRC Plenaries
- Kinam Kim:
Future silicon technology. 1-6 - Maurizio Zuffada:
The industrialization of the Silicon Photonics: Technology road map and applications. 7-13 - Nan Sun, Yong Liu, Ling Qin, Guangyu Xu
, Donhee Ham
Solid-state and biological systems interface. 14-17 - Liam Madden, Ephrem Wu
Advancing high performance heterogeneous integration through die stacking. 18-24 - Max Christian Lemme
Graphene for microelectronics: Can it make a difference? 25-27
ESSCIRC Plenary
- Kevin Zhang:
Challenges and opportunities for circuit design in nano-scale CMOS technologies. 28-29
Joint ESSDERC/ESSCIRC Session on Compact Modeling
- Yogesh Singh Chauhan
BSIM - Industry standard compact MOSFET models. 30-33 - Maria-Anna Chalkiadaki, Anurag Mangla, Christian C. Enz, Yogesh Singh Chauhan
Evaluation of the BSIM6 compact MOSFET model's scalability in 40nm CMOS technology. 34-37 - Benjamin Dormieu, Patrick Scheer, Clement Charbuillet, Sebastien Jan, François Danneville
4-Port isolated MOS modeling and extraction for mmW applications. 38-41
Joint ESSDERC/ESSCIRC Session on Variablity / Reliability
- Tobias Gemmeke
Variability aware cell library optimization for reliable sub-threshold operation. 42-45 - Bertrand Ardouin, Jean-Yves Dupuy, Jean Godin, Virginie Nodjiadjim, Muriel Riet, François Marc, Gilles Amadou Koné, Sudip Ghosh
Advancements on reliability-aware analog circuit design. 46-52
Digital Transmitters
- Shuichi Fukuda, Shinji Miya, Miho Io, Koichi Hamashita, Bram Nauta
Direct-digital modulation (DIDIMO) transmitter with -156dBc/Hz Rx-band noise using FIR structure. 53-56 - Shiyuan Zheng, Howard C. Luong
A WCDMA/WLAN digital polar transmitter with AM replica feedback linearization in 65nm CMOS. 57-60 - Silvian Spiridon, Johan van der Tang, Han Yan, Hua-feng Chen:
A 375 mW, 2.2 GHz signal bandwidth DAC-based transmitter with an in-band IM3 <-58 dBc in 40 nm CMOS. 61-64 - Filippo Borlenghi, Ernst Martin Witte, Gerd Ascheid, Heinrich Meyr, Andreas Burg
A 2.78 mm2 65 nm CMOS gigabit MIMO iterative detection and decoding receiver. 65-68
Amplifiers
- Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi:
A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. 69-72 - Qinwen Fan, Johan H. Huijsing, Kofi A. A. Makinwa:
A capacitively-coupled chopper operational amplifier with 3μV Offset and outside-the-rail capability. 73-76 - María de Rodanas Valero
A 0.8-V 1.2-μW rail-to-rail fully differential OpAmp with adaptive biasing. 77-80 - Jiawei Xu, Qinwen Fan, Johan H. Huijsing, Chris Van Hoof
Measurement and analysis of input current noise in chopper amplifiers. 81-84
CMOS Optical Sensors
- Edward M. D. Fisher
A reconfigurable 14-bit 60GPhoton/s Single-Photon receiver for visible light communications. 85-88 - Shingo Mandai, Vishwas Jain, Edoardo Charbon:
A fully-integrated 780×800μm2 multi-digital silicon photomultiplier with column-parallel time-to-digital converter. 89-92 - Matteo Perenzoni
A 160×160-pixel image sensor for multispectral visible, infrared and terahertz detection. 93-96 - Luca Sant
A system containing an ambient light and a proximity sensor with intrinsic ambient light rejection. 97-100
Energy Harvesting
- Joachim Leicht, Dominic Maurath, Yiannos Manoli:
Autonomous and self-starting efficient micro energy harvesting interface with adaptive MPPT, buffer monitoring, and voltage stabilization. 101-104 - Chao-Jen Huang, Wei-Chung Chen, Chia-Lung Ni, Ke-Horng Chen
Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking. 105-108 - Stefano Scorcioni, Alessandro Bertacchini
A 868MHz CMOS RF-DC power converter with -17dBm input power sensitivity and efficiency higher than 40% over 14dB input power range. 109-112 - Jens Masuch, Manuel Delgado-Restituto
An RF energy harvester with supply management for co-integration into a 2.4 GHz transceiver. 113-116
Receiver and Receiver Building Blocks
- Caroline Andrews, Changhyuk Lee, Alyosha C. Molnar:
Effects of LO harmonics and overlap shunting on N-phase passive mixer based receivers. 117-120 - Sumit Bagga, André Mansano, Wouter A. Serdijn, John R. Long, Kathleen Philips, John J. Pekarik:
A frequency-selective nested dual-loop broadband low-noise amplifier in 90 nm CMOS. 121-124 - Jaeyoung Choi, Donggu Im, Bum-Kyum Kim, Kwyro Lee:
Hardware-efficient non-decimation RF sampling receiver front-end with reconfigurable FIR filtering. 125-128 - Gerben W. de Jong, Domine Leenaerts, Edwin van der Heijden:
A fully integrated down-converter for Ka-band VSAT satellite reception. 129-132 - Jorge Hermosillo, Jorge Carballido, Arturo Veloz-Guerrero, David Arditti, Alberto Del Rio, Edgar Borrayo Sandoval, Manuel E. Guzman-Renteria, Hasnain Lakdawala, Marian Verhelst
A programmable calibration/BIST engine for RF/analog blocks in SoCs. 133-136
Circuit Design in Emerging Technologies
- Aravind Heragu, David Ruffieux, Christian C. Enz:
A 2.4-GHz MEMS-based PLL-free multi-channel receiver with channel filtering at RF. 137-140 - Daniele Raiteri, Fabrizio Torricelli
A synchronous rail-to-rail latched comparator based on double-gate organic thin-film-transistors. 141-144 - Sahel Abdinia, Mohamed Benwadih
Design of analog and digital building blocks in a fully printed complementary organic technology. 145-148 - Yiqun Wang, Yongpan Liu, Shuangchen Li, Daming Zhang, Bo Zhao, Mei-Fang Chiang, Yanxin Yan, Baiko Sai, Huazhong Yang:
A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops. 149-152 - Fady Abouzeid
28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder. 153-156
Multiple Output Converters
- Chia-Min Chen, Te-Wen Liao, Kai-Hsiu Hsu, Chung-Chih Hung:
A single-inductor multiple-output boost converter with freewheel charge-pump control. 157-160 - Yu-Huei Lee, Tzu-Chi Huang, Kuan-Yu Chu, Chao-Chang Chiu, Ke-Horng Chen
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS. 161-164 - Yonggen Liu, Chenchang Zhan, Wing-Hung Ki
A fast-transient-response hybrid buck converter with automatic and nearly-seamless loop transition for portable applications. 165-168 - Nico De Clercq, Tom Van Breussegem, Wim Dehaene, Michiel Steyaert
Dual-output capacitive DC-DC converter with power distribution regulator in 90 nm CMOS. 169-172
High Throughput Digital Architectures
- Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall:
A 0.8 mm2 9.6 mW implementation of a multicarrier Faster-than-Nyquist signaling iterative decoder in 65nm CMOS. 173-176 - Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh
A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. 177-180 - Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung:
A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. 181-184 - Seiryu Sasaki, Masahiro Yasuda, Hans Jürgen Mattausch:
Digital associative memory for word-parrallel Manhattan-distance-based vector quantization. 185-188
PLLs and Frequency Synthesizers
- Alan W. L. Ng, Shiyuan Zheng, Howard C. Luong
A 4.1GHz-6.5GHz all-digital frequency synthesizer with a 2nd-order noise-shaping TDC and a transformer-coupled QVCO. 189-192 - Hyung Seok Kim, Carlos Ornelas, Kailash Chandrashekar, Pin-en Su, Paolo Madoglio, Yee William Li, Ashoke Ravi:
A digital fractional-N PLL with a 3mW 0.004mm2 6-bit PVT and mismatch insensitive TDC. 193-196 - Theodore R. Blank, Per Torstein Røine, Jan-Tore Marienborg, Sudipto Chakraborty, Joerg Ackermann, Edward P. Coleman, Joel A. Zolnier, C. Bulla, P. Kristoffersen, Walter A. Budziak, Patrick Seem, Kevin Faison, Torjus Kallerud, Arne Nettum, Chiang-Hua Yeh:
A low power low phase noise fractional-N synthesizer with linearization and mismatch noise shaping techniques for sub-GHz multi-band transceiver with narrow channel spacing. 197-200 - Wei Deng, Teerachot Siriburanon
A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. 201-204
Oversampled ADCs
- Jesus Guinea, Enrico Sentieri, Andrea Baschirotto
An instrumentation 128dB-SNR 750μA SDM. 205-208 - Thomas Christen:
A 15bit 140μW scalable-bandwidth inverter-based audio ΔΣ modulator with >78dB PSRR. 209-212 - Pieter Rombouts
A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits. 213-216 - Ali Zahabi, Muhammad Anis, Maurits Ortmanns:
A 9.6 GS/s 112 mW 58 dB DR 150 MHz bandwidth RF bandpass transmission line ΣΔ modulator. 217-220
Wireline Transceivers
- Dan Li, Gabriele Minoia
A 25Gb/s low noise 65nm CMOS receiver tailored to 100GBASE-LR4. 221-224 - Kamran Farzan, Mehrdad Ramezani, Angus McLaren, Roman Pahuta, Nadeesha Amarasinghe, David Cassan, Saman Sadr:
A low jitter 2.7mW/Gbps 180Gb/s 12-lane transmitter in a 40nm CMOS technology. 225-228 - Sumantra Seth, Jayesh Wadekar:
A differential self-biased slew rate controlled driver for accurate cross-over and rise-fall time matching. 229-232 - Hyo-Gyuem Rhew, Michael P. Flynn, JunYoung Park:
A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. 233-236
CMOS Sensor Systems
- Dong-Hyuk Lim, Jun-Eun Park
A low-noise differential front-end and its controller for capacitive touch screen panels. 237-240 - Imran Ahmed, David Halupka, Bertram Leesti, James A. Cherry, Robert McKenzie, Alireza Nilchi, Hamed Mazhab-Jafari, W. Martin Snelgrove, Raymond Chik:
A 3-axis PZT-based MEMS gyroscope in 0.18μm CMOS. 241-244 - Frédéric Rothan, Cyril Condemine, Bertrand Delaet, Olivier Redon, Alain Giraud:
A low power 16-channel fully integrated GMR-based current sensor. 245-248 - Siddharth Seth, Shasha Wang, Thomas W. Kenny, Boris Murmann
A -131-dBc/Hz, 20-MHz MEMS oscillator with a 6.9-mW, 69-kΩ, gain-tunable CMOS TIA. 249-252
Analog - Timing
- Kenta Sogo, Akihiro Toya, Takamaro Kikkawa:
A ring-VCO-based sub-sampling PLL CMOS circuit with -119 dBc/Hz phase noise and 0.73 ps jitter. 253-256 - Ravi Mehta, Sumantra Seth, Siddharth Shashidharan, Biman Chattopadhyay, Sujoy Chakravarty:
A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process. 257-260 - Valentijn De Smedt
A 127 μW exact timing reference for Wireless Sensor Networks based on injection locking. 262-264
Data Converter Techniques
- Rui Wang, U-Fat Chio, Sai-Weng Sin
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. 265-268 - Nan Sun, Hae-Seung Lee, Donhee Ham
A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration. 269-272 - Jussi-Pekka Jansson
A multi-channel wide range time-to-digital converter with better than 9ps RMS precision for pulsed time-of-flight laser rangefinding. 273-276
Integrated Biomedical Systems
- Dai Jiang
An implantable 3-D vestibular stimulator with neural recording. 277-280 - Karim Abdelhalim, Hamed Mazhab-Jafari, Larysa Kokarovtseva, José Luis Pérez Velazquez, Roman Genov:
64-Channel UWB wireless neural vector analyzer and phase synchrony-triggered stimulator SoC. 281-284 - Kyong-Ho Lee, Naveen Verma:
A 1.2-0.55V general-purpose biomedical processor with configurable machine-learning accelerators for high-order, patient-adaptive monitoring. 285-288
mmWave Signal Generation
- Yan Zhao, Janus Grzyb, Ullrich R. Pfeiffer
A 288-GHz lens-integrated balanced triple-push source in a 65-nm CMOS technology. 289-292 - Xiang Yi, Chirn Chye Boon
A 100 GHz transformer-based varactor-less VCO with 11.2% tuning range in 65nm CMOS technology. 293-296 - Liang Wu, Howard C. Luong
A 49-to-62GHz CMOS quadrature VCO with bimodal enhanced magnetic tuning. 297-300
Power / Data Telemetry for Biomedical Systems
- Dominik Cirmirakis, Dai Jiang
A fast passive phase shift keying modulator for inductively coupled implanted medical devices. 301-304 - Tuan Vu Cao, Christoph Maier
BFSK MICS direct-DCO transmitter with adaptive background frequency regulation. 305-308 - Hongcheng Xu, Emilia Noorsal, Kriangkrai Sooksood
A multichannel neurostimulator with transcutaneous closed-loop power control and self-adaptive supply. 309-312
Low-voltage SRAMs
- Sylvain Clerc, Fady Abouzeid
A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance. 313-316 - Yasue Yamamoto, Atsushi Kawasumi, Shinichi Moriwaki, Toshikazu Suzuki, Shinji Miyano, Hirofumi Shinohara:
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations. 317-320 - Pascal Andreas Meinerzhagen, Oskar Andersson
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. 321-324
Converter Regulators
- Piet Callemeyn, Michiel Steyaert
Monolithic integration of a class DE inverter for on-chip resonant DC-DC converters. 325-328 - Thomas Jackum, Wolfgang Pribyl, Frank Praemassing, Gerhard Maderbacher, Roman Riederer:
Capacitor-less LVR for a 32-bit automotive microcontroller SoC in 65nm CMOS. 329-332 - Danzhu Lu, Jiale Yu, Zhiliang Hong, Jingwen Mao, Hui Zhao, Eric Cirot:
A 10MHz ripple-based on-time controlled buck converter with dual ripple compensation and real-time efficiency optimization. 333-336
RF Power Amplifiers
- Dixian Zhao, Shailesh Kulkarni, Patrick Reynaert
A 60 GHz dual-mode power amplifier with 17.4 dBm output power and 29.3% PAE in 40-nm CMOS. 337-340 - Wagdy M. Gaber, Piet Wambacq, Jan Craninckx
A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. 341-344 - Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya:
2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm. 345-348 - Hiroyuki Nakamoto, Masahiro Kudo, Kimitoshi Niratsuka, Toshihiko Mori, Shinji Yamaura
A real-time temperature-compensated CMOS RF on-chip power detector with high linearity for wireless applications. 349-352
RF Receivers
- Matteo Bassi
A 1.75-15 GHz stepped frequency receiver for breast cancer imaging in 65 nm CMOS. 353-356 - Lars Sundström
Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS. 357-360 - Mark S. Oude Alink
Improving harmonic rejection for spectrum sensing using crosscorrelation. 361-364 - Chen Jiang, Junren Liu, Yumei Huang, Zhiliang Hong:
A low-noise, 8.95-11GHz all-digital frequency synthesizer with a metastability-free time-to-digital converter and a sleepy counter in 65nm CMOS. 365-368
SAR ADCs
- Dai Zhang, Atila Alvandpour:
A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s. 369-372 - Pieter Harpe, Guido Dolmans, Kathleen Philips, Harmke de Groot:
A 0.7V 7-to-10bit 0-to-2MS/s flexible SAR ADC for ultra low-power wireless sensor nodes. 373-376 - Guohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin
A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. 377-380 - Kentaro Yoshioka
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. 381-384
Sensor Interface & Monitoring Circuits
- Gaurav Singh, Rong Wu, Youngcheol Chae, Kofi A. A. Makinwa:
A 20bit continuous-time ΣΔ modulator with a Gm-C integrator, 120dB CMRR and 15 ppm INL. 385-388 - Edoardo Bonizzoni, Aldo Pena-Perez, Hervé Caracciolo, David Stoppa, Franco Maloberti:
An incremental ADC sensor interface with input switch-Less integrator featuring 220-nVrms resolution with ±30-mV input range. 389-392 - Changsun Baek, Chaeyeol Lim, Daeyun Kim, Minkyu Song:
Design of a 10-bit CMOS image sensor based on an 8-bit configurable hold-and-go counter. 393-397 - Nathalie Deltimple, José Luis González, Josep Altet
Design of a fully integrated CMOS self-testable RF power amplifier using a thermal sensor. 398-401
VCOs
- Fabio Padovan, Marc Tiebout, Koen L. R. Mertens, Andrea Bevilacqua
A SiGe bipolar VCO for backhaul E-band communication systems. 402-405 - Luca Fanori, Pietro Andreani:
Low-phase-noise 3.4-4.5 GHz dynamic-bias class-C CMOS VCOs with a FoM of 191 dBc/Hz. 406-409 - Takahiro Nakamura, Takayasu Norimatsu, Toshiya Uozumi, Keisuke Ueda, Taizo Yamawaki:
A Δ∑-modulator-less digitally-controlled oscillator using fractional capacitors for GSM/EDGE transmitter. 410-413
Analog A
- Xicheng Jiang, Min-Gyu Kim, Felix Cheung, Fang Lin, Hui Zheng, Jianlong Chen, Alex Jianzhong Chen, Darwin Cheung, Khaled Abdelfattah, Seong-Ho Lee, Hanson Hung-Sen Huang, Kishore Kasichainula, Yonghua Cong, Jiangfeng Wu, Chang-Hyeon Lee, George Chih, Yun Tu, Todd Brooks, Edison Jiang, Hongwei Kong, Chaoyang Zhao, Mustafa Keskin:
A 40 nm CMOS analog front end with enhanced audio for HSPA/EDGE multimedia applications. 414-417 - Daniel Gruber
A high-input-swing common-mode-robust programmable gain amplifier in 65nm CMOS. 418-421 - Remy Cellier, Angelo Nagari, Souha Hacine, Gaël Pillonnet
A synchronized self oscillating Class-D amplifier for mobile application. 422-425
Low Power Techniques
- Cui Zhou, Pieter Harpe, Xiaoyan Wang, Kathleen Philips, Harmke de Groot:
10ns Start-up techniques for a duty cycled Impulse Radio receiver. 426-429 - Maarten Lont, Dusan M. Milosevic, Arthur H. M. van Roermund, Guido Dolmans:
Ultra-low power FSK receiver for body area networks with automatic frequency control. 430-433 - Jesse Richmond, Mervin John, Louis P. Alarcón, Wenting Zhou, Wen Li, Tsung-Te Liu, Massimo Alioto, Seth Sanders, Jan M. Rabaey:
Active RFID: Perpetual wireless communications platform for sensors. 434-437
High Voltage and Lighting
- Hans Meyvaert, Patrick Smeets, Michiel Steyaert
A 265VRMS mains interface integrated in 0.35μm CMOS. 438-441 - Yi-Ping Su, Shao-Wei Chiu, Chun-Chieh Kuo, Yu-Huei Lee, Ke-Horng Chen
Inductorless and electrolytic capacitorless pseudo-sine current controller in LED lighting system with 1.1W/2.2W power reduction. 442-445 - Se-Won Wang, Young-Jin Woo, Gyu-Ha Cho, Gyu-Hyeong Cho:
Emulated multi-path PID compensator for buck converters with large step-down ratio. 446-449
Processors and Serial Links
- Gyeonghoon Kim, Jinwook Oh, Hoi-Jun Yoo:
A 86mW 98GOPS ANN-searching processor for Full-HD 30fps video object recognition with zeroless locality-sensitive hashing. 450-453 - Jae-Wook Kwon, Xuefan Jin
A 3.0 Gb/s clock data recovery circuits based on digital DLL for clock-embedded display interface. 454-457 - Socrates D. Vamvakos, Bendik Kleveland, Dipak K. Sikdar, B. K. Ahuja, Haidang Lin, Jayaprakash Balachandran, Wignes Balakrishnan, Aldo Bottelli, Jawji Chen, Xiaole Chen, Jae Choi, Jeong Choi, Rajesh Chopra, Sanjay Dabral, Kalyan Dasari, Ronald B. David, Shaishav Desai, Claude R. Gauthier, Mahmudul Hassan, Kuo-Chiang Hsieh, Ramosan Canagasaby, Jeff Kumala, E. P. Kwon, Ben Lee, Ming Liu, Gurupada Mandal, Sundari Mitra, Byeong Cheol Na, Siddharth Panwar, Jay Patel, Chethan Rao, Vithal Rao, Richard Rouse, Ritesh Saraf, Subramanian Seshadri, Jae-K. Sim, Clement Szeto, Alvin Wang, Jason Yeung:
A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. 458-461
Analog B
- Young-sub Yuk, Seungchul Jung, Byunghun Lee, Se-Won Wang, Chul Kim, Gyu-Hyeong Cho:
A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process. 462-465 - Richard Jan Engel Jansen, Johan Haanstra, David Sillars Greenpeak:
Complementary constant-gm biasing of Nauta-transconductors in low-power gm-C filters to +/-2% accuracy over temperature. 466-469 - Martin Anderson, Roland Strandberg, Staffan Ek, Leif R. Wilhelmsson, Lars Sundström
A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS. 470-473
Nanometer Digital Circuit Techniques
- Nele Reynders, Wim Dehaene:
Variation-resilient sub-threshold circuit solutions for ultra-low-power Digital Signal Processors with 10MHz clock frequency. 474-477 - Yejoong Kim
SLC: Split-control Level Converter for dense and stable wide-range voltage conversion. 478-481 - Frank Leong, Robert Rutten, Nenad Pavlovic, Amine Mounaim:
A 6.5 GHz Arbitrary Digital Waveform Generator. 482-485 - Roel Maes
Experimental evaluation of Physically Unclonable Functions in 65 nm CMOS. 486-489
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