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21. ACM Great Lakes Symposium on VLSI 2012: Salt Lake City, UT, USA
- Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang:
Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake City, UT, USA, May 3-4, 2012. ACM 2012, ISBN 978-1-4503-1244-8
Keynote address
- Al Davis:
The role of photonics in future data centers. 1-2
Emerging technologies
- Kotb Jabeur, Ian O'Connor
, Nataliya Yakymets, Sébastien Le Beux:
Ambipolar double-gate FETs for the design of compact logic structures. 3-8 - Mahmoud Zangeneh, Ajay Joshi:
Performance and energy models for memristor-based 1T1R RRAM cell. 9-14 - Alessandro Vincenzi, Arvind Sridhar, Martino Ruggiero, David Atienza:
Accelerating thermal simulations of 3D ICs with liquid cooling using neural networks. 15-20 - Sadiq M. Sait, Abdalrahman M. Arafeh:
Efficient CMOL nanoscale hybrid circuit cell assignment using simulated evolution heuristic. 21-26
Reliability
- Varadaraj Kamath Nileshwar, Roman Lysecky:
SNR analysis approach for hardware/software partitioning using dynamically adaptable fixed point representation. 27-32 - Simone Corbetta, William Fornaciari
NBTI mitigation in microprocessor designs. 33-38 - Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. 39-44 - Jifeng Chen, Shuo Wang, Mohammad Tehranipoor:
Efficient selection and analysis of critical-reliability paths and gates. 45-50
Poster session 1
- Kaushik Mazumdar, Mircea R. Stan
Breaking the power delivery wall using voltage stacking. 51-54 - Osman Allam, Stijn Eyerman, Lieven Eeckhout:
An efficient CPI stack counter architecture for superscalar processors. 55-58 - Libo Huang, Zhiying Wang, Nong Xiao:
An optimized multicore cache coherence design for exploiting communication locality. 59-62 - Manohar Ayinala, Keshab K. Parhi
Parallel pipelined FFT architectures with reduced number of delays. 63-66 - Piotr Patronik, Krzysztof S. Berezowski, Janusz Biernat, Stanislaw J. Piestrak, Aviral Shrivastava
Design of an RNS reverse converter for a new five-moduli special set. 67-70 - Andrea Acquaviva, Nicola Bombieri
On the automatic synthesis of parallel SW from RTL models of hardware IPs. 71-74 - Jin-Tai Yan, Ming-Chien Huang, Zhi-Wei Chen:
Top-down-based symmetrical buffered clock routing. 75-78 - Keisuke Inoue, Mineo Kaneko:
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis. 79-82 - HeungJun Jeon, Yong-Bin Kim:
A fully integrated switched-capacitor DC-DC converter with dual output for low power application. 83-86 - Laurent Bousquet, Emmanuel Simeu:
High-level modeling of power consumption in active linear analog circuits. 87-90 - Kyundong Kim, Seidai Takeda, Shinobu Miwa, Hiroshi Nakamura
A novel power-gating scheme utilizing data retentiveness on caches. 91-94 - Nicholas Tuzzio, Kan Xiao, Xuehui Zhang, Mohammad Tehranipoor:
A zero-overhead IC identification technique using clock sweeping and path delay analysis. 95-98 - Jiajia Jiao, Yuzhuo Fu:
RAPA: reliability-aware priority arbitration strategy for network on chip. 99-102 - Daniel T. Grissom, Philip Brisk
A high-performance online assay interpreter for digital microfluidic biochips. 103-106 - Masoud Zamani, Mehdi Baradaran Tahoori:
Reliable logic mapping on Nano-PLA architectures. 107-110
Circuit design
- Jing Yang, Yong-Bin Kim:
Self adaptive body biasing scheme for leakage power reduction in nanoscale CMOS circuit. 111-116 - Ying Teng, Baris Taskin:
Synchronization scheme for brick-based rotary oscillator arrays. 117-122 - Pengpeng Chen, Bo Zhao, Rong Luo, Huazhong Yang:
A low-power all-digital GFSK demodulator with robust clock data recovery. 123-128 - Renatas Jakushokas, Eby G. Friedman:
Link breaking methodology: mitigating noise within power networks. 129-134
CAD-I
- Luís Guerra e Silva
Unifying functional and parametric timing verification. 135-140 - Huan Chen, João Marques-Silva
New & improved models for SAT-based bi-decomposition. 141-146 - Curtis Andrus, Matthew R. Guthaus
Lithography-aware layout compaction. 147-152 - Aroua Briki, Cyrille Chavet, Philippe Coussy, Eric Martin:
A design approach dedicated to network-based and conflict-free parallel interleavers. 153-158
Multi-core and NOC
- Jia Zhao, Russell Tessier, Wayne P. Burleson:
Distributed sensor data processing for many-cores. 159-164 - Sujay Deb
CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links. 165-170 - Kan Wang
Voltage island-driven power optimization for application specific network-on-chip design. 171-176 - David Brenner, Cory E. Merkel, Dhireesha Kudithipudi:
Design-time performance evaluation of thermal management policies for SRAM and RRAM based 3D MPSoCs. 177-182
Testing and fault-tolerance
- Shuo Wang, Mohammad Tehranipoor:
TSUNAMI: a light-weight on-chip structure for measuring timing uncertainty induced by noise during functional and test operations. 183-188 - Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov:
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. 189-194 - Dominik Gruber, Timm Ostermann:
Influence of different layout styles on the performance of the calibration of an on-chip programmable voltage reference. 195-200 - Saman Kiamehr, Farshad Firouzi, Mehdi Baradaran Tahoori:
Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates. 201-206
Keynote address
- Khaled N. Salama
Memristor: the illusive device. 207-208
Post-CMOS circuits
- Joseph S. Friedman, Nikhil Rangaraju, Yehea I. Ismail, Bruce W. Wessels:
InMnAs magnetoresistive spin-diode logic. 209-214 - Sajib Kumar Mitra, Lafifa Jamal
An efficient approach for designing and minimizing reversible programmable logic arrays. 215-220 - Fabrizio Lombardi, Wei Wei, Jie Han:
Modeling a single electron turnstile in HSPICE. 221-226 - Arne Heittmann, Tobias G. Noll:
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits. 227-232
Low power
- Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura
Stepwise sleep depth control for run-time leakage power saving. 233-238 - Santhosh Kumar Rethinagiri, Rabie Ben Atitallah, Jean-Luc Dekeyser, Eric Senn, Smaïl Niar:
An efficient power estimation methodology for complex RISC processor-based platforms. 239-244 - Bojan Maric, Jaume Abella
ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. 245-250 - In-Seok Jung, Yong-Bin Kim:
A low stand-by power start-up circuit for SMPS PWM controller. 251-254
Poster session 2
- Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng:
Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL. 255-258 - Amlan Ganguly, Mohsin Yusuf Ahmed, Anuroop Vidapalapati:
A denial-of-service resilient wireless NoC architecture. 259-262 - Jacob Murray, John Klingner, Partha Pratim Pande, Behrooz A. Shirazi:
Sustainable multi-core architecture with on-chip wireless links. 263-266 - Zhe Zhang, Michael A. Turi, José G. Delgado-Frias:
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells. 267-270 - Zaid Al-bayati, Otmane Aït Mohamed, Syed Rafay Hasan, Yvon Savaria:
A novel hybrid FIFO asynchronous clock domain crossing interfacing method. 271-274 - Jin-Tai Yan, Jun-Min Chung, Zhi-Wei Chen:
Density-reduction-oriented layer assignment for rectangle escape routing. 275-278 - Wei Liu, Sandeep Miryala, Valerio Tenace
NBTI effects on tree-like clock distribution networks. 279-282 - Youenn Corre, Jean-Philippe Diguet, Dominique Heller, Loïc Lagadec
A framework for high-level synthesis of heterogeneous MP-SoC. 283-286 - Kamran Rahmani, Prabhat Mishra
Memory-based computing for performance and energy improvement in multicore architectures. 287-290 - Xi Li, Gangyong Jia, Yun Chen, Zongwei Zhu, Xuehai Zhou:
Share memory aware scheduler: balancing performance and fairness. 291-294 - Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri:
Alleviating NBTI-induced failure in off-chip output drivers. 295-298 - Jing Xie, Vijaykrishnan Narayanan, Yuan Xie:
Mitigating electromigration of power supply networks using bidirectional current stress. 299-302 - Marzieh Morshedzadeh, Ali Jahanian
Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage. 303-306 - Ashok Kumar Palaniswamy, Spyros Tragoudas:
A scalable threshold logic synthesis method using ZBDDs. 307-310 - Pilin Junsangsri, Fabrizio Lombardi:
A memristor-based TCAM (ternary content addressable memory) cell: design and evaluation. 311-314
CAD-II
- Peter M. Maurer:
Extending symmetric variable-pair transitivities using state-space transformations. 315-320 - Fuqiang Qian, Haitong Tian, Evangeline F. Y. Young:
Crosslink insertion for variation-driven clock network construction. 321-326 - Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert:
WRIP: logic restructuring techniques for wirelength-driven incremental placement. 327-332 - Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty:
STEP: a unified design methodology for secure test and IP core protection. 333-338
VLSI systems
- Agathoklis Papadopoulos, Vasilis J. Promponas
Towards systolic hardware acceleration for local complexity analysis of massive genomic data. 339-344 - Seungcheol Baek
A dual-phase compression mechanism for hybrid DRAM/PCM main memory architectures. 345-350 - Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov:
Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration. 351-356 - Sayed Ahmad Salehi, Rassoul Amirfattahi, Keshab K. Parhi
Efficient folded VLSI architectures for linear prediction error filters. 357-362 - Kamran Rahmani, Hadi Hajimiri, Kartik Shrivastava, Prabhat Mishra
Synergistic integration of code encryption and compression in embedded systems. 363-368
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