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ASP-DAC 1997: Chiba, Japan
- Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997. IEEE 1997, ISBN 0-7803-3663-1
- Tsunemasa Hayashi, Atsushi Takahara, Ken-nosuke Fukami:
Co-evaluation of FPGA architectures and the CAD system for telecommunication. 1-8 - Jang-Hyun Park, Yea-Chul Rho:
Performance test of Viterbi decoder for wideband CDMA system. 19-23 - Yutaka Tamiya:
Delay estimation for technology independent synthesis. 31-36 - Atsushi Takahashi
, Yoji Kajitani:
Performance and reliability driven clock scheduling of sequential logic circuits. 37-42 - Kwang-Su Seong, Chong-Min Kyung:
CBLO: a clustering based linear ordering for netlist partitioning. 43-48 - Dirk Behrens, Erich Barke, Robert Tolkiehn:
Design driven partitioning. 49-55 - Masahiro Sano, Shintaro Shimogori, Fumiyasu Hirose:
Acceleration of mincut partitioning using hardware CAD accelerator TP5000. 61-64 - Youn-Long Lin:
Computing brokerage and its application in VLSI design. 65-69 - Shun Morikawa, Keisuke Okada, Sumitaka Takeuchi, Isao Shirakawa:
A high performance FIR filter dedicated to digital video transmission. 77-82 - Chauchin Su, Kathy Y. Chen, Shyh-Jye Jou:
Structural approach for performance driven ECC circuit synthesis. 89-94 - Chi-Hong Hwang, Allen C.-H. Wu:
An entropy measure for power estimation of Boolean functions. 101-106 - Kai Zhang, Haruhiko Takase, Terumine Hayashi, Hidehiko Kita:
An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits. 107-112 - Jyh-Mou Tseng, Jing-Yang Jou:
A power driven two-level logic optimizer. 113-116 - Qing Wu, Massoud Pedram, Xunwei Wu:
A note on the relationship between signal probability and switching activity. 117-120 - Fang-Jou Liu, John Lillis, Chung-Kuan Cheng:
A new layout-driven timing model for incremental layout optimization. 127-131 - Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
Par-POPINS: a timing-driven parallel placement method with the Elmore delay model for row based VLSIs. 133-140 - Peter B. Denyer, Jean Brouwers:
JavaTM in electronic design automation. 141-144 - Ing-Jer Huang, Li-Rong Wang, Yu-Min Wang:
Synthesis and analysis of an industrial embedded microcontroller. 151-156 - Massimo Bombana, Patrizia Cavalloro, Fabrizio Ferrandi
Property verification in the design of telecom applications. 167-172 - Joon-Seo Yim, Chang-Jae Park, Woo-Seung Yang, Hun-Seung Oh, Hee-Choul Lee, Hoon Choi, Tae-Hoon Kim, Seungjong Lee, Nara Won, Yung-Hei Lee, In-Cheol Park
Verification methodology of compatible microprocessors. 173-180 - Vida Vakilotojar, Peter A. Beerel:
RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking. 181-188 - Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu:
CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits. 189-194 - Sri Parameswaran, Hui Guo:
Power consumption in CMOS combinational logic blocks at high frequencies. 195-200 - Youcef Bourai, Nouma Izeboudjen, Yacine Bouhabel, Amine Tafat:
A new approach for an AHDL based on system semantics. 201-206 - Werner John:
EMC-adequate design of printed circuit boards as a part of the system development. 207-214 - Tetsuhisa Mido, Kunihiro Asada:
Crosstalk noise in high density and high speed interconnections due to inductive coupling. 215-220 - Toshimasa Watanabe:
MULTI-PRIDE: a system for supporting multi-layered printed wiring board design. 221-226 - Abderrazek Jemai, Polen Kission, Ahmed Amine Jerraya:
Embedded architectural simulation within behavioral synthesis environment. 227-232 - Wei-Liang Ing, Cheng-Tsung Hwang, Allen C.-H. Wu:
Evaluating cost-performance tradeoffs for system level applications. 233-238 - Youn-Sik Hong, Choong-Hee Cho, Daniel D. Gajski:
A quantitative analysis for optimizing memory allocation. 239-245 - M. Kanecko, Jialin Tian:
Concurrent cell generation and mapping for CMOS logic circuits. 247-252 - Gueesang Lee:
Logic synthesis for cellular architecture FPGAs using BDDs. 253-258 - Jie-Hong R. Jiang, Jing-Yang Jou, Juinn-Dar Huang, Jung-Shian Wei:
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture. 259-264 - Maggie Zhiwei Kang, Wayne Wei-Ming Dai:
General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing grid structure. 265-270 - Jonathan Dufour, Robert McBride, Ping Zhang, Chung-Kuan Cheng:
A building block placement tool. 271-276 - Tianming Kong, Xianlong Hong, Changge Qiao:
VEAP: Global optimization based efficient algorithm for VLSI placement. 277-280 - Rajaesh K. Gupta:
Hardware-software co-design: Tools for architecting systems-on-a-chip. 285-289 - Claudio Passerone, Luciano Lavagno, Claudio Sansoè, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli:
Trade-off evaluation in embedded system design via co-simulation. 291-297 - Tommy King-Yin Cheung, Graham R. Hellestrand, Prasert Kanthamanon:
A transformational codesign methodology. 299-305 - Katsuyuki Takabatake, Toshimitsu Masuzawa, Michiko Inoue, Hideo Fujiwara:
Non-scan design for testable data paths using thru operation. 313-318 - C.-J. Richard Shi:
Block-level fault isolation using partition theory and logic minimization techniques. 319-324 - Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. 329-332 - Wenming Zhou, Zeyi Wang, Lan Rao:
Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements. 339-343 - Won-Cheol Choi, Hirobumi Kawashima, Ryo Dang:
Simulation of gate switching characteristics of a miniaturized MOSFET based on a non-isothermal non-equilibrium transport model. 345-348 - Chong-Min Kyung, In-Cheol Park
Multi-project chip activities in Korea-IDEC perspective. 353-357 - Jen-Sheng Hwang:
Multi-project chip service for university and industry in Taiwan. 359-363 - Yoshiyuki Ito, Yuichi Nakamura:
A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface. 377-382 - Jinian Bian, Hongxi Xue, Ming Su:
VIDE: a visual VHDL integrated design environment. 383-386 - Takayuki Morimoto, Kazushi Saito, Hiroshi Nakamura, Taisuke Boku, Kisaburo Nakazawa:
Advanced processor design using hardware description language AIDL. 387-390 - Radu Marculescu, Diana Marculescu
Adaptive models for input data compaction for power simulators. 391-396 - Wang-Dauh Tseng, Kuochen Wang:
Fuzzy-based circuit partitioning in built-in current testing. 397-400 - Jürgen Schrage:
Modeling and detection of dynamic errors due to reflection- and crosstalk-noise. 405-408 - Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama:
Low-power multiple-valued current-mode integrated circuit with current-source control and its application. 413-418 - Kyoohyun Lim, Seung Hee Choi, Beomsup Kim:
Optimal loop bandwidth design for low noise PLL applications. 425-428 - Tokinori Kozawa:
Collaboration between university and industry. 433 - Min Xu, Fadi J. Kurdahi:
ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications. 435-440 - Tsuyoshi Isshiki, Wayne Wei-Ming Dai, Hiroaki Kunieda:
Bit-serial pipeline synthesis and layout for large-scale configurable systems. 441-446 - Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen:
AQUILA: An equivalence verifier for large sequential circuits. 455-460 - Bernd Becker, Rolf Drechsler, Reinhard Enders:
On the representational power of bit-level and word-level decision diagrams. 461-467 - Nicole Göckel, Rolf Drechsler, Bernd Becker:
Learning heuristics for OKFDD minimization by evolutionary algorithms. 469-472 - Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura:
On properties of Kleene TDDs. 473-476 - Makiko Okumura, Hiroshi Tanimoto:
A time-domain method for numerical noise analysis of oscillators. 477-482 - Jaijeet S. Roychowdhury, Peter Feldmann:
A new linear-time harmonic balance algorithm for cyclostationary noise analysis in RF circuits. 483-492 - Koutaro Hachiya
Enhancement of parallelism for tearing-based circuit simulation. 493-498 - Peter Marwedel:
Processor-core based design and test. 499-502 - Masayuki Yamaguchi, Akihisa Yamada, Toshihiro Nakaoka, Takashi Kambe:
Architecture evaluation based on the datapath structure and parallel constraint. 503-508 - Natesan Venkateswaran, Anurag Gupta, Srinivas Katkoori
A constructive method for data path area estimation during high-level VLSI synthesis. 509-515 - Qing Wu, Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram:
Statistical design of macro-models for RT-level power evaluation. 523-528 - Dominik Stoffel, Wolfgang Kunz, Stefan Gerber:
AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks. 529-538 - Yibin Ye, Kaushik Roy:
Efficient synthesis of AND/XOR networks. 539-544 - Debatosh Debnath, Tsutomu Sasao:
An optimization of AND-OR-EXOR three-level networks. 545-550 - Massoud Pedram, Xunwei Wu:
A new description of CMOS circuits at switch-level. 551-556 - Shunji Saika, Masahiro Fukui, Noriko Shinomiya, Toshiro Akino:
A two-dimensional transistor placement for cell synthesis. 557-562 - Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen, Tsair-Chin Lin:
DP-Gen: a datapath generator for multiple-FPGA applications. 563-568 - Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs. 569-578 - Yu-Liang Wu, Douglas Chang, Malgorzata Marek-Sadowska, Shuji Tsukiyama:
Not necessarily more switches more routability [sic.]. 579-584 - Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee:
On the control-subroutine implementation of subprogram synthesis. 587-592 - Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
A procedure for software synthesis from VHDL models. 593-598 - Peter Marwedel, Birger Landwehr, Rainer Dömer:
Built-in chaining: introducing complex components into architectural synthesis. 599-605 - De-Sheng Chen, Majid Sarrafzadeh:
Cube-embedding based state encoding for low power design. 613-618 - Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani:
A mapping from sequence-pair to rectangular dissection. 625-633 - C.-J. Richard Shi:
Solving constrained via minimization by compact linear programming. 635-640 - Naoyuki Iso, Yasushi Kawaguchi, Tomio Hirata:
Efficient routability checking for global wires in planar layouts. 641-644 - Toshiyuki Hama, Hiroaki Etoh:
Topological routing path search algorithm with incremental routability test. 645-648 - Chong-Min Kyung, In-Cheol Park
HK386: an x86-compatible 32-bit CISC microprocessor. 661-662 - Kazuo Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi:
Super low power 8-bit CPU with pass-transistor logic. 663-664 - Kazutoshi Kobayashi, Masayoshi Kinoshita, Masahiro Takeuchi, Hidetoshi Onodera, Keikichi Tamaru:
A functional memory type parallel processor for vector quantization. 665-666 - Kazuhito Ito, Takenobu Shimizugashira, Hiroaki Kunieda:
High speed bit-serial parallel processing on array architecture. 667-668 - Tin-Chak Johnson Pang, Oliver Chiu-sing Choy, Cheong-Fat Chan, Wai-kuen Cham:
Self-timed 1-D ICT processor. 669-670 - Fahad M. Alzahrani, Tom Chen:
A real-time high performance edge detector for computer vision applications. 671-672 - Takayuki Kamei, Masashi Sasahara, Hideharu Amano:
An LSI implementation of the simple serial synchronized multistage interconnection network. 673-674 - Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh:
The RDT network router chip. 675-676 - Joon-Seo Yim, Hee-Choul Lee, Tae-Hoon Kim, Bong-Il Park, Chang-Jae Park, In-Cheol Park
Single cycle access cache for the misaligned data and instruction prefetch. 677-678 - Takumi Nakano, Yoshiki Komatsudaira, Akichika Shiomi, Masaharu Imai:
VLSI implementation of a real-time operating system. 679-680 - Yong-Bin Kim, Tom Chen:
A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps. 681-682 - Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
A current mode cyclic A/D converter with a 0.8 μm CMOS process. 683-684 - Yasuhiro Sugimoto, Tetsuya Iida:
A current-mode, 3 V, 20 MHz, 9-bit equivalent CMOS sample-and-hold circuit. 685-686
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