default search action
4th ASYNC 1998: San Diego, CA, USA
- 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA. IEEE Computer Society 1998, ISBN 0-8186-8392-9
SUN
- William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland:
A FIFO Data Switch Design Experiment. 4-
Microprocessor I
- Marc Renaudin, Pascal Vivet
, Frédéric Robin:
ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor. 22-31 - Nigel C. Paver, Paul Day, Craig Farnsworth, Dave L. Jackson
A Low-Power, Low-Noise, Configurable Self-Timed DSP. 32-42 - Martin Benes, Steven M. Nowick, Andrew Wolfe:
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors. 43-
Synthesis and Tech Map
- Michael Theobald, Steven M. Nowick:
An Implicit Method for Hazard-Free Two-Level Logic Minimization. 58-69 - Kevin W. James, Kenneth Y. Yun:
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. 70-79 - Wei-Chun Chou, Peter A. Beerel, Ran Ginosar, Rakefet Kol, Chris J. Myers, Shai Rotem, Ken S. Stevens, Kenneth Y. Yun:
Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. 80-
Microprocessor II
- Hans van Gageldonk, Kees van Berkel, Ad M. G. Peeters, Daniel Baumann, Daniel Gloor, Gerhard Stegmann:
An Asynchronous Low-Power 80C51 Microcontroller. 96-107 - Kåre Tais Christensen, Peter Jensen, Peter Korger, Jens Sparsø
The Design of an Asynchronous TinyRISCTM TR4101 Microprocessor Core. 108-
Interconnect
- W. J. Bainbridge, Stephen B. Furber:
Asynchronous Macrocell Interconnect using MARBLE. 122-132 - Per Torstein Røine:
An Asynchronous PRBS Error Checker for Testing High-Speed Self-Clocked Serial Links. 133-
Verification
- Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet:
Verifying a Self-Timed Divider. 146-158 - Radu Negulescu, Ad M. G. Peeters:
Verification of Speed-Dependences in Single-Rail Handshake Circuits. 159-
Formal Methods
- Tom Verhoeff
Analyzing Specifications for Delay-Insensitive Circuits. 172-183 - Willem C. Mallon, Jan Tijmen Udding:
Building Finite Automata from DI Specifications. 184-193 - Stanislaw J. Piestrak:
Membership Test Logic for Delay-Insensitive Codes. 194-
Signal Processing
- D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. Gao:
Towards Asynchronous A-D Conversion. 206-215 - Bruce W. Hunt, Kenneth S. Stevens, Bruce W. Suter, Donald S. Gelosh:
A Single Chip Low Power Asynchronous Implementation of an FFT Algorithm for Space Applications. 216-223 - Ross Smith, Karl Fant, Dave Parker, Rick Stephani, Ching-Yi Wang:
An Asynchronous 2-D Discrete Cosine Transform Chip. 224-
Performance Analysis
- Jo C. Ebergen, Scott Fairbanks, Ivan E. Sutherland:
Predicting Performance of Micropipelines Using Charlie Diagrams. 238-246 - Aiguo Xie, Peter A. Beerel:
Accelerating Markovian Analysis of Asynchronous Systems using String- based State Compression. 247-
RSFQ
- Yoshio Kameda, Stanislav Polonsky, Masaaki Maezawa
Primitive-Level Pipelining Method on Delay-Insensitive Model for RSFQ Pulse-Driven Logic. 262-273 - Z. John Deng, Steve R. Whiteley, Theodore Van Duzer, José A. Tierno:
Asynchronous Circuits and Systems in Superconducting RSFQ Digital Technology. 274-
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-12-19 22:02 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: