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PACT 2007: Brasov, Romania
- 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007. IEEE Computer Society 2007, ISBN 0-7695-2944-5
Hardware Track (Session 1): Systems
- Jayanth Gummaraju, Mattan Erez
, Joel Coburn, Mendel Rosenblum, William J. Dally:
Architectural Support for the Stream Execution Model on General-Purpose Processors. 3-12 - Miquel Pericàs, Adrián Cristal, Francisco J. Cazorla, Rubén González, Daniel A. Jiménez, Mateo Valero:
A Flexible Heterogeneous Multi-Core Architecture. 13-24 - Alexandra Fedorova, Margo I. Seltzer, Michael D. Smith:
Improving Performance Isolation on Chip Multiprocessors via an Operating System Scheduler. 25-38
Software Track (Session 2): Pipelining
- Alban Douillet, Guang R. Gao:
Software-Pipelining on Multi-Core Architectures. 39-48 - Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August:
Speculative Decoupled Software Pipelining. 49-59 - Suhyun Kim, Soo-Mook Moon:
Rotating Register Allocation for Enhanced Pipeline Scheduling. 60-72
Hardware Track (Session 3): Verification & Security
- Martin Dimitrov, Huiyang Zhou:
Unified Architectural Support for Soft-Error Protection or Software Bug Detection. 73-82 - Anita Lungu, Daniel J. Sorin:
Verification-Aware Microprocessor Design. 83-93 - Manhee Lee, Minseon Ahn, Eun Jung Kim:
I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems. 94-103 - Albert Meixner, Daniel J. Sorin:
Error Detection Using Dynamic Dataflow Verification. 104-118
Software Track (Session 4): Optimizations
- Kelly Heffner, David Tarditi, Michael D. Smith:
Extending Object-Oriented Optimizations for Concurrent Programs. 119-129 - Lingli Zhang, Chandra Krintz, Priya Nagpurkar:
Language and Virtual Machine Support for Efficient Fine-Grained Futures in Java. 130-139 - Priya Nagpurkar, Harold W. Cain, Mauricio J. Serrano, Jong-Deok Choi, Chandra Krintz:
Call-chain Software Instruction Prefetching in J2EE Server Applications. 140-149 - Nitzan Peleg, Bilha Mendelson:
Detecting Change in Program Behavior for Adaptive Optimization. 150-162
Hardware Track (Session 5): Saving Energy
- Guangyu Chen, Feihui Li, Mahmut T. Kandemir:
Reducing Energy Consumption of On-Chip Networks Through a Hybrid Compiler-Runtime Approach. 163-174 - Ronald G. Dreslinski, Bo Zhai, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester:
An Energy Efficient Parallel Architecture Using Near Threshold Operation. 175-188
Software Track (Session 6): Algorithms
- Hiroshi Inoue, Takao Moriyama, Hideaki Komatsu, Toshio Nakatani:
AA-Sort: A New Parallel Sorting Algorithm for Multi-Core SIMD Processors. 189-198 - Xuejun Yang, Yunfei Du, Panfeng Wang, Hongyi Fu, Jia Jia, Zhiyuan Wang, Guang Suo:
The Fault Tolerant Parallel Algorithm: the Parallel Recomputing Based Failure Recovery. 199-212
Hardware Track (Session 7): Processors
- Brian Greskamp, Josep Torrellas:
Paceline: Improving Single-Thread Performance in Nanoscale CMPs through Core Overclocking. 213-224 - Eduardo Quiñones, Joan-Manuel Parcerisa, Antonio González:
Early Register Release for Out-of-Order Processors with RegisterWindows. 225-234 - Yoav Etsion, Dror G. Feitelson:
L1 Cache Filtering Through Random Selection of Memory References. 235-244 - Nauman Rafique, Won-Taek Lim, Mithuna Thottethodi:
Effective Management of DRAM Bandwidth in Multicore Processors. 245-258
Software Track (Session 8): Compilers
- Jeremy Lau, Matthew Arnold, Michael Hind, Brad Calder:
A Loop Correlation Technique to Improve Performance Auditing. 259-269 - Xiaofeng Guo, Jinquan Dai, Long Li, Zhiyuan Lv, Prashant R. Chandra:
Latency Hiding in Multi-Threading and Multi-Processing of Network Applications. 270-279 - Jaewook Shin:
Introducing Control Flow into Vectorized Code. 280-291 - Nicolas Vasilache, Albert Cohen, Louis-Noël Pouchet:
Automatic Correction of Loop Transformations. 292-304
Hardware Track (Session 9): Modeling & Measurement
- Javier Vera, Francisco J. Cazorla, Alex Pajuelo, Oliverio J. Santana, Enrique Fernández, Mateo Valero:
FAME: FAirly MEasuring Multithreaded Architectures. 305-316 - John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu:
CIGAR: Application Partitioning for a CPU/Coprocessor Architecture. 317-326 - Salman Khan, Polychronis Xekalakis, John Cavazos, Marcelo Cintra:
Using PredictiveModeling for Cross-Program Design Space Exploration in Multicore Systems. 327-338 - Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Jaideep Moses, Srihari Makineni, Donald Newell:
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. 339-352
Software Track (Session 10): Transactional Memory & Locks
- Richard L. Halpert, Christopher J. F. Pickett, Clark Verbrugge:
Component-Based Lock Allocation. 353-364 - Marek Olszewski, Jeremy Cutler, J. Gregory Steffan:
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory. 365-375 - Woongki Baek, Chi Cao Minh, Martin Trautmann, Christos Kozyrakis, Kunle Olukotun:
The OpenTM Transactional Application Programming Interface. 376-387 - Ian Watson, Chris C. Kirkham, Mikel Luján:
A Study of a Transactional Parallel Routing Algorithm. 388-398
Poster Abstracts
- Sayaka Akioka, Feihui Li, Mahmut T. Kandemir, Padma Raghavan, Mary Jane Irwin:
Ring Prediction for Non-Uniform Cache Architectures. 401 - Yosi Ben-Asher, Moshe Yuda:
Source Level Merging of Independent Programs. 402 - Florina M. Ciorba, Ioannis Riakiotakis, George K. Papakonstantinou, Theodore Andronikos, Anthony T. Chronopoulos:
Studying the impact of synchronization frequency on scheduling tasks with dependencies in heterogeneous systems. 403 - Lionel Damez, Jean-Pierre Dérutin:
Fast prototyping of complex Signal and Image Processing applications on SoC using homogenous network of communicating processors. 404 - Abhishek Das, William J. Dally:
Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. 405 - Stijn Eyerman, Lieven Eeckhout, James E. Smith:
Studying Compiler-Microarchitecture Interactions through Interval Analysis. 406 - John Giacomoni, Tipp Moseley, Manish Vachharajani:
FastForward for Efficient Pipeline Parallelism. 407 - Sven Groot, Harmen L. A. van der Spek, Erwin M. Bakker, Harry A. G. Wijshoff:
The Automatic Transformation of Linked List Data Structures. 408 - Marco Höbbel, Thomas Rauber, Carsten Scholtes:
Trace-based Automatic Padding for Locality Improvement with Correlative Data Visualization Interface. 409 - Changjun Hu, Jilin Zhang, Jue Wang, Jianjiang Li, Liang Ding:
A New Parallel Gauss-Seidel Method by Iteration Space Alternate Tiling. 410 - Costin Iancu, Wei Chen, Katherine A. Yelick:
Performance Portable Optimizations for Loops Containing Communication Operations. 411 - Ajay M. Joshi, Lieven Eeckhout, Lizy Kurian John:
Exploring the Application Behavior Space Using Parameterized Synthetic Benchmarks. 412 - Simo Juvaste:
Studying Asynchronous Shared Memory Computations. 413 - Kirk Kelsey, Chengliang Zhang, Chen Ding:
Fast Track: Supporting Unsafe Optimizations with Software Speculation. 414 - Minhaj Ahmad Khan, Henri-Pierre Charles, Denis Barthou:
Hybrid Specialization: A Trade-off Between Static and Dynamic Specialization. 415 - Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares:
Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. 416 - Georgiana Macariu, Marc Frîncu, Alexandru Cârstea, Dana Petcu, Andrei Eckstein:
Redesigning Parallel Symbolic Computations Packages. 417 - Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
MLP-Aware Dynamic Cache Partitioning. 418 - Cosmin E. Oancea, Alan Mycroft:
A Lightweight Model for Software Thread-Level Speculation (TLS). 419 - Kostas Papadopoulos, Kyriakos Stavrou, Pedro Trancoso:
HelperCore_DB: Exploiting Multicore Technology for Databases. 420 - Lazaros Papadopoulos, Christos Baloukas, Dimitrios Soudris, Konstantinos Potamianos, Nikolaos S. Voros:
Data Structure Exploration of Dynamic Applications. 421 - Kaushik Rajan, Ramaswamy Govindarajan, Bharadwaj Amrutur:
Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. 422 - Tanausú Ramírez, Alex Pajuelo, Oliverio J. Santana, Mateo Valero:
Runahead Threads: Reducing Resource Contention in SMT Processors. 423 - Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, Sule Ozev:
Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation. 424 - Harald Servat, Cecilia Gonzalez, Xavier Aguilar, Daniel Cabrera, Daniel Jiménez-González
Drug Design on the Cell BroadBand Engine. 425 - Xipeng Shen, Feng Mao:
Bridging Inputs and Program Dynamic Behavior. 426 - Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Power-Aware Compiler Controllable Chip Multiprocessor. 427 - Jaswanth Sreeram, Romain Cledat, Tushar Kumar, Santosh Pande
RSTM : A Relaxed Consistency Software Transactional Memory for Multicores. 428 - Rafael Ubal, Julio Sahuquillo, Salvador Petit
VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. 429 - Rajesh Vivekanandham, R. Govindarajan:
A Scalable Low Power Store Queue for Large InstructionWindow Processors. 430 - Philip M. Wells, Koushik Chakraborty, Gurindar S. Sohi:
Adapting to Intermittent Faults in Future Multicore Systems. 431 - Matthew A. Watkins, Sally A. McKee, Lambert Schaelicke:
A Phase-Adaptive Approach to Increasing Cache Performance. 432 - Jing Yu, María Jesús Garzarán:
Compiler Optimizations for Fault Tolerance Software Checking. 433 - Weihua Zhang, Tao Bao, Binyu Zang, Chuanqi Zhu:
Optimizing Bandwidth Constraint through Register Interconnection for Stream Processors. 434
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