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"Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock ..."

Tejinder Singh Sandhu, Kamal El-Sankary (2019)

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DOI: 10.1109/TVLSI.2019.2894104

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/SandhuE19
Tejinder Singh Sandhu, Kamal El-Sankary:
Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures. IEEE Trans. Very Large Scale Integr. Syst. 27(6): 1480-1484 (2019)

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