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"Inductance model and analysis methodology for high-speed on-chip interconnect."

Kaushik Gala et al. (2002)

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DOI: 10.1109/TVLSI.2002.801619

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/GalaBZVJ02
Kaushik Gala, David T. Blaauw, Vladimir Zolotov, Pravin M. Vaidya, Anil Joshi:
Inductance model and analysis methodology for high-speed on-chip interconnect. IEEE Trans. Very Large Scale Integr. Syst. 10(6): 730-745 (2002)

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