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"8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global ..."

Jian-Wei Su et al. (2024)

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DOI: 10.1109/TCSII.2023.3331375

access: closed

type: Journal Article

metadata version: 2024-04-15

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  - journals/tcasII/SuLWCLCHRHCMLSLCHLLHTC24
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  - https://dblp.org/rec/journals/tcasII/SuLWCLCHRHCMLSLCHLLHTC24
Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang:
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2304-2308 (2024)

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