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"Two-stage low power test data compression for digital VLSI circuits."

K. Thilagavathi, S. Sivanantham (2018)

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DOI: 10.1016/J.COMPELECENG.2018.07.009

access: closed

type: Journal Article

metadata version: 2020-02-19

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K. Thilagavathi, S. Sivanantham:
Two-stage low power test data compression for digital VLSI circuits. Comput. Electr. Eng. 71: 309-320 (2018)

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