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"An External Memory Circuit Validation Algorithm for Large VLSI Layouts."

Yokesh Kumar, Prosenjit Gupta (2007)

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DOI: 10.1109/ISVLSI.2007.24

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
  - conf/isvlsi/KumarG07
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  - https://dblp.org/rec/conf/isvlsi/KumarG07
Yokesh Kumar, Prosenjit Gupta:
An External Memory Circuit Validation Algorithm for Large VLSI Layouts. ISVLSI 2007: 510-511

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