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"Delay analysis and optimal biasing for high speed low power Current Mode ..."

Vasanth Kakani, Foster F. Dai, Richard C. Jaeger (2004)

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DOI: —

access: unavailable

type: Conference or Workshop Paper

metadata version: 2016-05-20

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  dblp key:
  - conf/iscas/KakaniDJ04
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  - https://dblp.org/rec/conf/iscas/KakaniDJ04
Vasanth Kakani, Foster F. Dai, Richard C. Jaeger:
Delay analysis and optimal biasing for high speed low power Current Mode Logic circuits. ISCAS (2) 2004: 869-872

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