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"Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout ..."

Shusuke Yoshimoto et al. (2011)

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DOI: 10.1109/IOLTS.2011.5993829

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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  - conf/iolts/YoshimotoAKTYMYKY11
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  - https://dblp.org/rec/conf/iolts/YoshimotoAKTYMYKY11
Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156

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