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"An efficient gate delay model for VLSI design."

Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen (2007)

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DOI: 10.1109/ICCD.2007.4601938

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/iccd/ChiangCC07a
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  persistent URL:
  - https://dblp.org/rec/conf/iccd/ChiangCC07a
Ting Wei Chiang, C. Y. Roger Chen, Wei-Yu Chen:
An efficient gate delay model for VLSI design. ICCD 2007: 450-455

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