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"Gate sizing and buffer insertion for optimizing performance in power ..."

Kerry S. Lowe, P. Glenn Gulak (1993)

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DOI: 10.1109/ICCAD.1993.580059

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Kerry S. Lowe, P. Glenn Gulak:
Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits. ICCAD 1993: 216-219

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